The purpose of the EVT14 handler may depend on whether CONFIG_IPIPE is
enabled, albeit its implementation can be the same in both cases. When
the interrupt pipeline is enabled, EVT14 can be used to raise the core
priority level for the running code; when CONFIG_IPIPE is off, EVT14
can be used to lower this level before running softirq handlers.

Rename evt14_softirq to evt_evt14 to pick an identifier that fits
both, which allows to reuse the same vector setup code as well.
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The Blackfin arch has a bunch of custom section markings for its on-chip
regions, but they aren't declared in the right header.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

rename cache_lock() to bfin_cache_lock() to avoid namespace collision
with common code
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like

In this patch, we provide SMP extend to Blackfin header files
and machine common code
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

when copying L1 regions, go to the start of bss rather
than end since we have code to zero it out already
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Blackfin arch: bfin_reset() is an internal reboot function ... everyone should go through machine_restart()
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

avoid using actual config name in comment as a text search
is done to see what files need to be rebuilt
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Signed-off-by: NRobin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Signed-off-by: NBryan Wu <cooloney@kernel.org>

Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Blackfin arch: move fixed code defines into fixed_code.h as very few things actually need to know these details
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

 - remove cheesy read_iloc() function
 - move invalidate_entire_icache function to lock.S
 - export proper prototypes for functions in lock.S
 - only build lock.S when BFIN_ICACHE_LOCK is enabled
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Merge VR Regulator Hibernate wakeups into set_irq_wake for internal
interrupts.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

dont bother protecting the mtd defines as anything that incorrectly
uses it will get an error during link time anyways ... this prevents
large pointless rebuilds of most files whenever the uclinux mtd map changes state
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Extend system call to alloc L2 SRAM in application.
Automatically move following sections to L2 SRAM:
1. kernel built-in l2 attribute section
2. kernel module l2 attribute section
3. elf-fdpic application l2 attribute section
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

support two cascaded AD73322 cards, more uncached DMA
memory is needed, so add a choice to provide 4M DMA memory
Signed-off-by: NCliff Cai <cliff.cai@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

[Blackfin] arch: remove duplicated prototypes for internal cplb structures from the global blackfin header

remove duplicated prototypes for internal cplb structures from
the global blackfin header as nothing else should be accessing these
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Signed-off-by: NMeihui Fan <mhfan@hhcn.com>
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

 - Add support for irq_wake on system and gpio interrupts
 - Remove outdated kernel options
 - Add option to select default PM mode
 - Fix various places where SIC_IWRx was only handled partially
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Blackfin arch: split apart dump_bfin_regs and merge/remove show_regs from process.c, which was largely duplicated
Signed-off-by: NMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Signed-off-by: NMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Clean up dump_bfin_mem so that it will display
content from the kernel, as well as l1 instruction, when deferred
HW errors happen, print out the last frame info if it makes sense.
Signed-off-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

The only user is the a.out support.

It was therefore removed prior to the blackfin merge from all
architectures not supporting a.out.

Currently, Blackfin doesn't suppport a.out.
Signed-off-by: NAdrian Bunk <bunk@kernel.org>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Fix/change formatting of a few more things.
Signed-off-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Signed-off-by: NMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Blackfin arch: use "char bfin_board_name[]" rather than "char *bfin_board_name" per discussion on lkml as the former uses less storage
Signed-off-by: NMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Initialize the exception vectors early in the boot process, so that CPLB faults
can be handled when memory protection is enabled.
Signed-off-by: NBernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Blackfin arch: defines and provides entry points for certain user space functions at fixed addresses

This patch defines (and provides) entry points for certain user space functions
at fixed addresses.  The Blackfin has no usable atomic instructions, but we can
ensure that these code sequences appear atomic from a user space point of view
by detecting when we're in the process of executing them during the interrupt
handler return path.  This allows much more efficient pthread lock
implementations than the bfin_spinlock syscall we're currently using.

Also provided is a small sys_rt_sigreturn stub which can be used by the signal
handler setup code.  The signal.c part will be committed separately.
Signed-off-by: NBernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>

Blackfin arch: cache SWRST value at bootup so other things like watchdog can non-destructively query it
Signed-off-by: NMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix!  Tinyboards.

The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc.  (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000.  Since then ADI has put this core into its Blackfin
processor family of devices.  The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set.  It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.

The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf

The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc

This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/

We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel

[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: NBryan Wu <bryan.wu@analog.com>
Signed-off-by: NMariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: NAubrey Li <aubrey.li@analog.com>
Signed-off-by: NJie Zhang <jie.zhang@analog.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>