1. 04 11月, 2011 1 次提交
    • S
      powerpc/p3060qds: Add support for P3060QDS board · 96cc017c
      Shengzhou Liu 提交于
      The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
      The P3060 Processor combines six e500mc Power Architecture processor cores with
      high-performance datapath acceleration architecture(DPAA), CoreNet fabric
      infrastructure, as well as network and peripheral interfaces.
      
      P3060QDS Board Overview:
      Memory subsystem:
        - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
        - 128M Bytes NOR flash single-chip memory
        - 16M Bytes SPI flash
        - 8K Bytes AT24C64 I2C EEPROM
      Ethernet:
        - 4x1G + 4x1G/2.5G Ethernet controllers
        - 2xRGMII + 1xMII, three VSC8641 PHYs on board
        - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
      PCIe: Two PCI Express 2.0 controllers/ports
      USB:  Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
      I2C:  Four I2C controllers
      UART: Supports up to four UARTs
      RapidIO: Supports two serial RapidIO ports
      Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      96cc017c
  2. 12 10月, 2011 1 次提交
  3. 07 10月, 2011 1 次提交
    • M
      powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.c · d3133765
      Mingkai Hu 提交于
      There's only p2041rdb board for official release, but the p2041 silicon
      on the board can be converted to p2040 silicon without XAUI and L2 cache
      function, then the board becomes p2040rdb board. so we use the file name
      p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also
      consistent with the board name under U-Boot.
      
      During the rename we make few other minor changes to the device tree:
      * Move USB phy setting into p2041si.dtsi as its SoC not board defined
      * Convert PCI clock-frequency to decimal to be more readable
      Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      d3133765
  4. 23 9月, 2011 1 次提交
  5. 08 7月, 2011 1 次提交
    • M
      powerpc/85xx: Add p2040 RDB board support · 3fce1c0b
      Mingkai Hu 提交于
      P2040RDB Specification:
      -----------------------
      2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
      128 Mbyte NOR flash single-chip memory
      256 Kbit M24256 I2C EEPROM
      16 Mbyte SPI memory
      SD connector to interface with the SD memory card
      dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
      dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
      dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
      dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
      dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
      I2C1: Real time clock, Temperature sensor
      I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM
      SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
      UART: supports two UARTs up to 115200 bps for console
      USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
      PCIe:
       - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
       - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
      Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      3fce1c0b
  6. 27 6月, 2011 2 次提交
  7. 23 6月, 2011 1 次提交
  8. 14 10月, 2010 3 次提交
  9. 05 8月, 2010 1 次提交
  10. 20 4月, 2010 1 次提交
    • A
      powerpc/85xx/86xx: Fix build w/ CONFIG_PCI=n · e0f278ad
      Anton Vorontsov 提交于
      Currently some MPC85xx and MPC86xx boards fail to build without
      CONFIG_PCI:
      
      arch/powerpc/platforms/fsl_uli1575.c: In function 'quirk_final_uli5249':
      arch/powerpc/platforms/fsl_uli1575.c:234: error: implicit declaration of function 'pci_bus_for_each_resource'
      arch/powerpc/platforms/fsl_uli1575.c:234: error: expected ';' before '{' token
      cc1: warnings being treated as errors
      arch/powerpc/platforms/fsl_uli1575.c:223: warning: unused variable 'dummy'
      make[1]: *** [arch/powerpc/platforms/fsl_uli1575.o] Error 1
      
      This patch fixes the issue by appending 'if PCI' condition when
      selecting FSL_ULI1575 Kconfig symbol.
      Signed-off-by: NAnton Vorontsov <avorontsov@mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      e0f278ad
  11. 21 11月, 2009 2 次提交
  12. 25 8月, 2009 1 次提交
    • P
      powerpc/85xx: Add support for P2020RDB board · fb8e3e1f
      Poonam Aggrwal 提交于
      Add support for the P2020RDB reference board from Freescale.
      
      Overview of P2020RDB platform
      	- DDR
      	  DDR2 1G
      	- NOR Flash
      	  16MByte
      	- NAND Flash
      	  32MByte
      	- 3 Ethernet interfaces
      	  1) etSEC1
      		- RGMII
      		- connected to a 5 port Vitesse Switch(VSC7385)
      		- Switch is memory mapped through eLBC interface(CS#2)
      		- IRQ1
      	  2) etSEC2
      		- SGMII
      		- connected to VSC8221
      		- IRQ2
      	  3) etSEC3
      		- RGMII
      		- connected to VSC8641
      		- IRQ3
      	- 2 1X PCIe interfaces
      	- SD/MMC ,USB
      	- SPI EEPROM
      	- Serial I2C EEPROM
      Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      fb8e3e1f
  13. 16 6月, 2009 2 次提交
  14. 19 5月, 2009 1 次提交
  15. 27 3月, 2009 1 次提交
  16. 14 10月, 2008 1 次提交
  17. 17 7月, 2008 2 次提交
  18. 14 7月, 2008 1 次提交
  19. 10 6月, 2008 1 次提交
  20. 09 6月, 2008 1 次提交
    • K
      [POWERPC] 85xx: MPC85xx MDS - Unconditionally select PHYLIB for board fixups · c4ea8964
      Kumar Gala 提交于
      The MPC85xx MDS board requires some board level tweaks of the PHYs that
      either the eTSEC (gianfar) or UCC ethernet controllers are connected to.
      
      Its possible to build the phylib as a module, however this breaks the
      board level fix ups because phy_read and phy_write are not available
      if we build as a module.
      
      So we unconditionally select PHYLIB to ensure its built into the kernel
      if we are building in MPC85xx MDS support.  This was determined to be
      the easiest soultion even though it prevents the user from removing
      PHYLIB support if they decide they don't want it.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      c4ea8964
  21. 17 4月, 2008 1 次提交
  22. 27 3月, 2008 1 次提交
    • A
      [POWERPC] 85xx: Emerson KSI8560 base support · 22b619ee
      Alexandr Smirnov 提交于
      The KSI8560 is a single compact, mid-, or full-size Advanced Mezzanine Card
      (AdvancedMC™) based on the Freescale™ Semiconductor MPC8560 PowerQUICC III™
      microprocessor. This product will serve in data and signaling applications such
      as signaling gateways (SGW) and softswitch signaling interface cards.
      
      The board has altera maxii CPLD, that is used to obtain and manage board
      configuration. Also there are two SCC UART serial consoles and FCC ethernet,
      that is routed to the front panel, while other ethernet controlers (TSEC's) are
      routed to the backplane.
      Signed-off-by: NAlexandr Smirnov <asmirnov@ru.mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      22b619ee
  23. 29 1月, 2008 1 次提交
    • K
      [POWERPC] 85xx: rework platform Kconfig · 3a83156b
      Kumar Gala 提交于
      * Allow multiple boards to be selected in a single build
      * Removed Kconfig option '85xx' which existed only for compat with arch/ppc
      * Added a multiplatform 85xx defconfig (mpc85xx_defconfig). This builds
        all 85xx boards except sbc8560 and stx_gp3 since these to boards have
        board specific ifdef in driver code that may break all other boards
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      3a83156b
  24. 28 1月, 2008 5 次提交
  25. 11 10月, 2007 1 次提交
  26. 08 10月, 2007 1 次提交
  27. 14 9月, 2007 1 次提交
  28. 18 8月, 2007 1 次提交
    • K
      [POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards · b66510cb
      Kumar Gala 提交于
      The interrupt routing in the device trees for the ULI M1575 was
      inproperly using the interrupt line field as pci function.  Fixed
      up the device tree's to actual conform for to specification and
      changed the interrupt mapping code so it just uses a static mapping
      setup as follows:
      
      PIRQA - IRQ9
      PIRQB - IRQ10
      PIRQC - IRQ11
      PIRQD - IRQ12
      USB 1.1 OCHI (1c.0) - IRQ12
      USB 1.1 OCHI (1c.1) - IRQ9
      USB 1.1 OCHI (1c.2) - IRQ10
      USB 1.1 ECHI (1c.3) - IRQ11
      LAN (1b.0) - IRQ6
      AC97 (1d.0) - IRQ6
      Modem (1d.1) - IRQ6
      HD Audio (1d.2) - IRQ6
      SATA (1f.1) - IRQ5
      SMB (1e.1) - IRQ7
      PMU (1e.2) - IRQ7
      PATA (1f.0) - IRQ14/15
      
      Took the oppurtunity to refactor the code into a single file so we
      don't have to duplicate these fixes on the two current boards in the
      tree and several forth coming boards that will also need the code.
      
      Fixed RTC support that requires a dummy memory read on the P2P bridge
      to unlock the RTC and setup the default of the RTC alarm registers to
      match with a basic x86 style CMOS RTC.
      
      Moved code that poked ISA registers to a FIXUP_FINAL quirk to ensure
      the PCI IO space has been setup properly before we start poking ISA
      registers at random locations.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      b66510cb
  29. 24 7月, 2007 2 次提交