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  1. 07 1月, 2012 1 次提交
    • M
      PCI: Pull PCI 'latency timer' setup up into the core · 96c55900
      Myron Stowe 提交于
      The 'latency timer' of PCI devices, both Type 0 and Type 1,
      is setup in architecture-specific code [see: 'pcibios_set_master()'].
      There are two approaches being taken by all the architectures - check
      if the 'latency timer' is currently set between 16 and 255 and if not
      bring it within bounds, or, do nothing (and then there is the
      gratuitously different PA-RISC implementation).
      
      There is nothing architecture-specific about PCI's 'latency timer' so
      this patch pulls its setup functionality up into the PCI core by
      creating a generic 'pcibios_set_master()' function using the '__weak'
      attribute which can be used by all architectures as a default which,
      if necessary, can then be over-ridden by architecture-specific code.
      
      No functional change.
      Signed-off-by: NMyron Stowe <myron.stowe@redhat.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      96c55900
  2. 01 11月, 2011 1 次提交
  3. 31 3月, 2011 1 次提交
  4. 01 11月, 2010 1 次提交
    • P
      sh: machvec IO death. · 37b7a978
      Paul Mundt 提交于
      This takes a bit of a sledgehammer to the machvec I/O routines. The
      iomem case requires no special casing and so can just be dropped
      outright. This only leaves the ioport casing for PCI and SuperIO
      mangling. With the SuperIO case going through the standard ioport
      mapping, it's possible to replace everything with generic routines.
      
      With this done the standard I/O routines are tidied up and NO_IOPORT
      now gets default-enabled for the vast majority of boards.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      37b7a978
  5. 14 10月, 2010 1 次提交
    • P
      sh: pci: Support slot 4 routing on SDK7786. · 61a46766
      Paul Mundt 提交于
      SDK7786 supports connecting either slot3 or 4 to the same PCIe port by
      way of FPGA muxing. By default the vertical slot 3 on the baseboard is
      enabled, so this adds in a command line option for forcibly enabling the
      slot 4 edge connector.
      
      If nothing has been specified on the command line, we fall back to
      reading the resistor values for card presence to figure out where to
      route the port to.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      61a46766
  6. 20 9月, 2010 1 次提交
    • P
      sh: pci: Use a generic raw spinlock for PCI config access locking. · 39a90865
      Paul Mundt 提交于
      This copies the pci_config_lock idea from x86 over, allowing us to kill
      off a couple of existing private locks. At the same time, these need to
      be converted to raw spinlocks for -rt kernels, so we make that change at
      the same time. This should make it easier for future parts to get the
      locking right instead of inevitable ending up with lock type mismatches.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      39a90865
  7. 19 9月, 2010 1 次提交
  8. 07 6月, 2010 1 次提交
  9. 23 2月, 2010 2 次提交
  10. 03 2月, 2010 1 次提交
  11. 01 2月, 2010 4 次提交
  12. 29 1月, 2010 2 次提交
  13. 28 1月, 2010 1 次提交
  14. 24 8月, 2009 1 次提交
    • D
      sh: Allow use of GENERIC_IOMAP · 15444a89
      David McKay 提交于
      The synopsys PCI cell used in the later STMicro chips requires code to
      be run in order to do IO cycles, rather than just memory mapping the IO
      space. Rather than extending the existing SH infrastructure to allow
      this, use the GENERIC_IOMAP implmentation to save re-inventing the
      wheel.
      
      This set of changes allows the SH to be built with GENERIC_IOMAP
      enabled, it just ifdef's out the functions provided by the GENERIC_IOMAP
      implementation, and provides a few required missing functions.
      Signed-off-by: NDavid McKay <david.mckay@st.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      15444a89
  15. 16 6月, 2009 1 次提交
  16. 20 4月, 2009 10 次提交
  17. 16 4月, 2009 3 次提交
  18. 14 4月, 2009 1 次提交
  19. 08 1月, 2009 2 次提交
  20. 28 7月, 2008 1 次提交
  21. 28 6月, 2008 1 次提交
    • A
      PCI: remove unused arch pcibios_update_resource() functions · 0aea5313
      Adrian Bunk 提交于
      Russell King did the following back in 2003:
      
      <--  snip  -->
      
          [PCI] pci-9: Kill per-architecture pcibios_update_resource()
      
          Kill pcibios_update_resource(), replacing it with pci_update_resource().
          pci_update_resource() uses pcibios_resource_to_bus() to convert a
          resource to a device BAR - the transformation should be exactly the
          same as the transformation used for the PCI bridges.
      
          pci_update_resource "knows" about 64-bit BARs, but doesn't attempt to
          set the high 32-bits to anything non-zero - currently no architecture
          attempts to do something different.  If anyone cares, please fix; I'm
          going to reflect current behaviour for the time being.
      
          Ivan pointed out the following architectures need to examine their
          pcibios_update_resource() implementation - they should make sure that
          this new implementation does the right thing.  #warning's have been
          added where appropriate.
      
              ia64
              mips
              mips64
      
          This cset also includes a fix for the problem reported by AKPM where
          64-bit arch compilers complain about the resource mask being placed
          in a u32.
      
      <--  snip  -->
      
      This patch removes the unused pcibios_update_resource() functions the
      kernel gained since, from FRV, m68k, mips & sh architectures.
      Signed-off-by: NAdrian Bunk <bunk@kernel.org>
      Acked-by: NDavid Howells <dhowells@redhat.com>
      Acked-by: NGreg Ungerer <gerg@uclinux.org>
      Acked-by: NPaul Mundt <lethal@linux-sh.org>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      0aea5313
  22. 29 4月, 2008 1 次提交
  23. 28 1月, 2008 1 次提交