- 12 10月, 2016 1 次提交
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由 Ilia Mirkin 提交于
Tested on a NV34. There are reports of this also working on the other nv3x chips. Largely useful for testing software written for NV2x without having the actual hardware available. Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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- 30 7月, 2016 1 次提交
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由 Ilia Mirkin 提交于
This should fix some unaligned access warnings. This is also likely to fix non-descript issues on nv30/nv34 as a result of incorrect channel setup. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96836Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu> Cc: stable@vger.kernel.org Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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- 14 7月, 2016 4 次提交
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Julia Lawall 提交于
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Handle and propagate secure boot errors. Failure to do so results in Nouveau incorrectly believing init has succeeded and a completely black display during boot. If we propagate the error, GR init will fail and the user will at least have a working display. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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- 02 6月, 2016 1 次提交
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
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- 20 5月, 2016 16 次提交
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由 Ben Skeggs 提交于
This is a simplied version of the fix by Roy in fdo#93629. While this doesn't appear to fix the issues for the users in that report, it's a real issue that deserves to be resolved. Reported-by: NRoy Spliet <rspliet@eclipso.eu> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Also removes an XXX; according to nvgpu headers the field is called NV_PGRAPH_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3, so, apparently not some magic we need to figure out :) Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
This was really inconsistent, some implementations could touch PPCs that didn't exist, others neglected to touch ones that did. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Matches newer RM. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Later chipsets require setting this up both in FB and GR, so let's just move the allocation to FB. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Appears to more closely match what RM does. For GM20B, now also copying bit 12 from NV_PFB_MMU_CTRL as upcoming changes will require it. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
These are now specified directly in the MC subdev. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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- 22 4月, 2016 1 次提交
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
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- 14 3月, 2016 16 次提交
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由 Roy Spliet 提交于
It's supposed to always be 0, but at least nv_iowr() temporarily violates this. Since the ih touches $r0, it should be stored. Signed-off-by: NRoy Spliet <rs855@cam.ac.uk> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Secure falcons' firmware is managed by secboot. Do not load it in GR for them. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Start securely-managed falcons using secboot functions since the process for them is different from just writing CPUCTL. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Load firmware and bundles in GM200's constructor. The previously called GF100 function did not care about the bundles. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
There functions are going to be used by other chips that rely on NVIDIA-provided firmware. Export them. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Make these functions easier to use by handling memory management from within. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
The firmwares required by GR may vary from chip to chip, especially with the introduction of secure boot and NVIDIA-provided firmwares. Move the firmware loading outside of gf100_gr_ctor so other chips may still call it while managing their firmwares themselves. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Alexandre Courbot 提交于
Some members of gf100_gr were freed by the gk20a driver. That's not where it should be done - free them in gf100 so other chips that use NVIDIA-provided firmware free these structures properly. This also removes the need for a GK20A-specific destructor. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Most of the per-chipset differences will go away when we fully switch to using the register lists provided by the firmware files, which will leave all the remaining code "belonging" to GM200. This is a preemptive rename from GM204 to GM200. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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