1. 31 7月, 2014 1 次提交
    • J
      mlx5: Move pci device handling from mlx5_ib to mlx5_core · 9603b61d
      Jack Morgenstein 提交于
      In preparation for a new mlx5 device which is VPI (i.e., ports can be
      either IB or ETH), move the pci device functionality from mlx5_ib
      to mlx5_core.
      
      This involves the following changes:
      1. Move mlx5_core_dev struct out of mlx5_ib_dev. mlx5_core_dev
         is now an independent structure maintained by mlx5_core.
         mlx5_ib_dev now has a pointer to that struct.
         This requires changing a lot of places where the core_dev
         struct was accessed via mlx5_ib_dev (now, this needs to
         be a pointer dereference).
      2. All PCI initializations are now done in mlx5_core. Thus,
         it is now mlx5_core which does pci_register_device (and not
         mlx5_ib, as was previously).
      3. mlx5_ib now registers itself with mlx5_core as an "interface"
         driver. This is very similar to the mechanism employed for
         the mlx4 (ConnectX) driver. Once the HCA is initialized
         (by mlx5_core), it invokes the interface drivers to do
         their initializations.
      4. There is a new event handler which the core registers:
         mlx5_core_event(). This event handler invokes the
         event handlers registered by the interfaces.
      
      Based on a patch by Eli Cohen <eli@mellanox.com>
      Signed-off-by: NJack Morgenstein <jackm@dev.mellanox.co.il>
      Signed-off-by: NEli Cohen <eli@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9603b61d
  2. 28 5月, 2014 1 次提交
  3. 11 4月, 2014 1 次提交
  4. 08 3月, 2014 5 次提交
    • S
      IB/mlx5: Collect signature error completion · d5436ba0
      Sagi Grimberg 提交于
      This commit takes care of the generated signature error CQE generated
      by the HW (if happened).  The underlying mlx5 driver will handle
      signature error completions and will mark the relevant memory region
      as dirty.
      
      Once the consumer gets the completion for the transaction, it must
      check for signature errors on signature memory region using a new
      lightweight verb ib_check_mr_status().
      
      In case the user doesn't check for signature error (i.e. doesn't call
      ib_check_mr_status() with status check IB_MR_CHECK_SIG_STATUS), the
      memory region cannot be used for another signature operation
      (REG_SIG_MR work request will fail).
      Signed-off-by: NSagi Grimberg <sagig@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      d5436ba0
    • S
      IB/mlx5: Support IB_WR_REG_SIG_MR · e6631814
      Sagi Grimberg 提交于
      This patch implements IB_WR_REG_SIG_MR posted by the user.
      
      Baisically this WR involves 3 WQEs in order to prepare and properly
      register the signature layout:
      
      1. post UMR WR to register the sig_mr in one of two possible ways:
          * In case the user registered a single MR for data so the UMR data segment
            consists of:
            - single klm (data MR) passed by the user
            - BSF with signature attributes requested by the user.
          * In case the user registered 2 MRs, one for data and one for protection,
            the UMR consists of:
            - strided block format which includes data and protection MRs and
              their repetitive block format.
            - BSF with signature attributes requested by the user.
      
      2. post SET_PSV in order to set the memory domain initial
         signature parameters passed by the user.
         SET_PSV is not signaled and solicited CQE.
      
      3. post SET_PSV in order to set the wire domain initial
         signature parameters passed by the user.
         SET_PSV is not signaled and solicited CQE.
      
      * After this compound WR we place a small fence for next WR to come.
      
      This patch also introduces some helper functions to set the BSF correctly
      and determining the signature format selectors.
      Signed-off-by: NSagi Grimberg <sagig@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      e6631814
    • S
      IB/mlx5: Keep mlx5 MRs in a radix tree under device · 3bcdb17a
      Sagi Grimberg 提交于
      This will be useful when processing signature errors on a specific
      key.  The mlx5 driver will lookup the matching mlx5 memory region
      structure and mark it as dirty (contains signature errors).
      Signed-off-by: NSagi Grimberg <sagig@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      3bcdb17a
    • S
      IB/mlx5: Initialize mlx5_ib_qp signature-related members · e1e66cc2
      Sagi Grimberg 提交于
      If user requested signature enable we initialize relevant mlx5_ib_qp
      members.  We mark the qp as sig_enable and we increase the effective
      SQ size, but still limit the user max_send_wr to original size
      computed.  We also allow the create_qp routine to accept sig_enable
      create flag.
      Signed-off-by: NSagi Grimberg <sagig@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      e1e66cc2
    • S
      mlx5: Implement create_mr and destroy_mr · 3121e3c4
      Sagi Grimberg 提交于
      Support create_mr and destroy_mr verbs.  Creating ib_mr may be done
      for either ib_mr that will register regular page lists like
      alloc_fast_reg_mr routine, or indirect ib_mrs that can register other
      (pre-registered) ib_mrs in an indirect manner.
      
      In addition user may request signature enable, that will mean that the
      created ib_mr may be attached with signature attributes (BSF, PSVs).
      
      Currently we only allow direct/indirect registration modes.
      Signed-off-by: NSagi Grimberg <sagig@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      3121e3c4
  5. 14 2月, 2014 1 次提交
  6. 07 2月, 2014 1 次提交
    • E
      IB/mlx5: Fix binary compatibility with libmlx5 · 78c0f98c
      Eli Cohen 提交于
      Commit c1be5232 ("Fix micro UAR allocator") broke binary compatibility
      between libmlx5 and mlx5_ib since it defines a different value to the number
      of micro UARs per page, leading to wrong calculation in libmlx5. This patch
      defines struct mlx5_ib_alloc_ucontext_req_v2 as an extension to struct
      mlx5_ib_alloc_ucontext_req.  The extended size is determined in mlx5_ib_alloc_ucontext()
      and in case of old library we use uuarn 0 which works fine -- this is
      acheived due to create_user_qp() falling back from high to medium then to
      low class where low class will return 0.  For new libraries we use the
      more sophisticated allocation algorithm.
      Signed-off-by: NEli Cohen <eli@mellanox.com>
      Reviewed-by: NYann Droneaud <ydroneaud@opteya.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      78c0f98c
  7. 23 1月, 2014 5 次提交
  8. 15 1月, 2014 1 次提交
    • E
      IB/mlx5: Fix micro UAR allocator · c1be5232
      Eli Cohen 提交于
      The micro UAR (uuar) allocator had a bug which resulted from the fact
      that in each UAR we only have two micro UARs avaialable, those at
      index 0 and 1.  This patch defines iterators to aid in traversing the
      list of available micro UARs when allocating a uuar.
      
      In addition, change the logic in create_user_qp() so that if high
      class allocation fails (high class means lower latency), we revert to
      medium class and not to the low class.
      Signed-off-by: NEli Cohen <eli@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      c1be5232
  9. 09 11月, 2013 4 次提交
  10. 11 10月, 2013 3 次提交
  11. 16 8月, 2013 1 次提交
    • M
      net/mlx5_core: Support MANAGE_PAGES and QUERY_PAGES firmware command changes · 0a324f31
      Moshe Lazer 提交于
      In the previous QUERY_PAGES command version we used one command to get the
      required amount of boot, init and post init pages.  The new version uses the
      op_mod field to specify whether the query is for the required amount of boot,
      init or post init pages. In addition the output field size for the required
      amount of pages increased from 16 to 32 bits.
      
      In MANAGE_PAGES command the input_num_entries and output_num_entries fields
      sizes changed from 16 to 32 bits and the PAS tables offset changed to 0x10.
      
      In the pages request event the num_pages field also changed to 32 bits.
      
      In the HCA-capabilities-layout the size and location of max_qp_mcg field has
      been changed to support 24 bits.
      
      This patch isn't compatible with firmware versions < 5; however, it  turns out that the
      first GA firmware we will publish will not support previous versions so this should be OK.
      Signed-off-by: NMoshe Lazer <moshel@mellanox.com>
      Signed-off-by: NEli Cohen <eli@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0a324f31
  12. 06 8月, 2013 1 次提交
  13. 01 8月, 2013 1 次提交
    • E
      mlx5_core: Implement new initialization sequence · cd23b14b
      Eli Cohen 提交于
      Introduce enbale_hca and disable_hca commands to signify when the
      driver starts or ceases to operate on the device.
      
      In addition the driver will use boot and init pages count; boot pages
      is required to allow firmware to complete boot commands and the other
      to complete init hca.  Command interface revision is bumped to 4 to
      enforce using supported firmware.
      
      This patch breaks compatibility with old versions of firmware (< 4);
      however, the first GA firmware we will publish will support version 4
      so this should not be a problem.
      Signed-off-by: NEli Cohen <eli@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      cd23b14b
  14. 12 7月, 2013 1 次提交
  15. 09 7月, 2013 2 次提交