Consistently don't place a space after < or before >.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Cardhu's eMMC controller is on sdhci@78000600, not sdhci@78000400.
Fix the typo. This roughly doubles the IO performance, since the
support-8bit property actually takes effect.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Cc: stable@kernel.org # v3.4

Add device info for the core regulator tps62360 in tegra-cardhu
dts file.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed node name to reflect actual device type]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add a node for the Tegra30 SMMU
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add a node for the Tegra20 GART
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add Tegra MC(Memory Controller) nodes for tegra30.dtsi.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add Tegra MC(Memory Controller) nodes for tegra20.dtsi.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add AHB entry for tegra20/30.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

* Add node for the audio codec
* Enable Tegra's I2S1 controller and DAS
* Add node for top-level sound complex
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This is the micro-SD card slot.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

According to the device's datasheet, it can support an interrupt too.
However, the existing board file doesn't specify an interrupt, and I
don't have the schematics, so I can't add an interrupts property. The
current Linux driver doesn't support anyway.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the known i2c devices on seaboard to the i2c table.

Also rename the temperature sensor device node, and mark it as a nct1008
instead of an adt7461 (which it is -- the chips are compatible though).
Signed-off-by: NOlof Johansson <olof@lixom.net>
[swarren: Removed isl29018 from patch; it's already there now. Fixed
 interrupts properties now that Tegra GPIO is an interrupt controller.
 Moved smart-battery to the correct I2C bus.]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The I2C2 controller can be routed to either pingroup DDC or PTA. Seaboard
actually uses this as an I2C bus mux, and devices are connected to both
pingroups. This change statically assigns the I2C2 controller to pingroup
PTA, so that on-board devices can be accessed. The DDC pingroup is used
for EDID/DDC accesses which are not yet required, given the absence of
any Tegra graphics support. I2C muxing will be supported later.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the device info for ALS and proximity sensor for tegra
boards cardhu, ventana and seaboard.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: s/PZ02/PZ2/ in .dts files, s/seabridge/seaboard/ in commit
 description]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Ensure that the USB ULPI signals are not tri-stated, and have no pull-
up or pull-down.

Ensure that the pingroup hosting the USB ULPI reset signal (GPIO PV0 or
PV1 depending on the board, so UAC) is not tri-stated, and has no pull-
up or pull-down.

This change appears larger than it is due to the grouping and sorting of
the pin configuration data.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.

I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.

Cc: <devicetree-discuss@lists.ozlabs.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add WM8903 codec nodes, and top-level sound complex node for basic
analog audio over headset jack and internal speakers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Add nodes for the Tegra30 AHUB and I2S controllers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

This adds a complete pinmux configuration to all Tegra20 device tree
files. This allows removal of board-dt-tegra20.c's use of the pinmux
board files, and the special device tree handling in board-pinmux.c.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

This adds a minimal pinmux configuration to the Tegra Cardhu device
tree. Initially, just the built-in eMMC and SD card slot are configured.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net

These were incorrectly introduced and can cause problems for of_irq_init.

The correct way to define a root controller is no interrupt-parent set at
all or the interrupt-parent is set to the root controller itself when
inherited from a parent node.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Tested-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Because of the inclusion of skeleton.dtsi, the memory node is
named "memory" we where not modifying the already included one
but creating a new one. It caused bad memory node detection during
early_init_dt_scan_memory() so we modify them.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Change vbus gpio configuration in .dts files to switch to
active low configuration.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: stable <stable@vger.kernel.org>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently the following devices
are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600
evaluation board, with nearly zero peripheral devices (only UART
and GPIO), it makes sense to switch over to DT based configuration
completely now. So this patch also removes all non-DT stuff, mainly
platform device data. The files spear600.c and spear600_evb.c are
removed completely.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This enables local timer (AKA: private timer) support for
all u8500 based hardware using DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This SSP Controller supports a number of serial communication methods
and as such cannot be registered using of_register_spi_devices.
Instead we register it simply as a primecell device.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Enables the 3 UARTs found on a u8500 using DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This enables the embedded GIC on all u8500 based hardware using DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This adds all devices that are normally present through the
u8500_init_machine function in the device tree as well, which
will duplicate the devices that are visible.

This will not do much by itself because the device from the
device tree are not matched by any device driver until they
are converted as well. The next step is to move over one
device at a time to actually be used from the device tree
instead of the hardcoded device using auxdata to pass the
correct platform_data.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

db8500.dtsi can be used by all systems with a db8500 or
db9500 SoC, while snowball.dts is board specific.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This provides very basic Device Tree support for ST-Ericsson's
low-cost development platform, Snowball. If Device Tree for
ux500 is enabled and the correct board is configured within the
Device Tree blob, the correct *_init_machine() will be called.

This patch is based on some original work completed by:
  Niklas Hernaeus <niklas.hernaeus@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NNiklas Hernaeus <niklas.hernaeus@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Define both uarts in kirkwood.dtsi as they are common to all kirkwood
SoCs.  Each board may enable all or none of them, so they are disabled
by default.  uart0 is enabled for the dreamplug.

tclk can vary for each board, so we leave it undefined in the kirkwood
dtsi.  Each board can then set it as appropriate when enabling the uart.
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Also, use inclusive register size for uart0.
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

make the ECHI depends on ARCH_AT91
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: devicetree-discuss@lists.ozlabs.org

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: devicetree-discuss@lists.ozlabs.org