Remove unused #address-cells and #size-cells from pinmux
node. This fixes W=1 warnings of the type:

arch/arm/boot/dts/da850-lcdk.dtb: Warning (avoid_unnecessary_addr_size): /soc@1c00000/pinmux@14120: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

Tested on DA850 LCDK by checking output of:

/sys/kernel/debug/pinctrl/1c14120.pinmux-pinctrl-single/pins

before and after the change.
Reviewed-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

skeleton.dtsi is deprecated. Drop its usage in da850.dtsi
and move the nodes and properties included by it directly
to keep the dtb same.

The memory node has been changed to get rid of warnings
(see below). It contains the memory base address as that is
fixed for DA850 SoCs. But the size needs to be added by
bootloader or a board specific dts.

This gets rid of the following W=1 warnings:

arch/arm/boot/dts/da850-enbw-cmc.dtb: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/da850-evm.dtb: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/da850-lego-ev3.dtb: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
Reviewed-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The TI Davinci DA8xx family of SoCs have a single DSP subsystem
that is comprised of TI's standard TMS320C674x megamodule and
several blocks of internal memory (L1P, L1D and L2 RAMs). Add
the DT node for this DSP processor sub-system. The processor
does not have an MMU, and uses a chip-level signalling register
and shared memory for inter-processor communication with the
ARM core.

The node has been added in disabled state, and can be enabled
in the respective board dts file with an associated reserved
memory block.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The gpio node has 144 gpios. Each gpio is capable of generating
an interrupt. Hence add interrupt-controller property to the gpio
node. With this in place one can use interrupts property in device
tree to request for the gpio interrupts.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This adds CPPI 4.1 DMA controller to USB OTG controller.

Changes since v2:
- Fixed the the property reg-names (had glue register defined)
- Removed few useless property
Signed-off-by: NAlexandre Bailon <abailon@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This moves the spi0_cs3_pin pinconf node from the LEGO EV3 file to the
common DA850 include file. This node is applicable to any board, and
therefore belongs in the common file.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Extend the vpif node with an output port with a single channel.

NOTE: this is still mostly just hardware description - the actual
driver is registered using pdata-quirks. We need the node however
for correct pin control function selection.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add a new pinctrl sub-node for vpif display pins. Move VP_CLKIN3 and
VP_CLKIN2 to the display node where they actually belong (vide section
36.2.2 of the OMAP-L138 technical reference manual).
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add the SATA node to the da850 device tree.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

TI DA8xx/OMAPL13x/AM17xx/AM18xx SoCs have extra UART registers beyond
the standard 8250 registers, so we need a new compatible string to
indicate this. Also, at least one of these registers uses the full 32
bits, so we need to specify reg-io-width in addition to reg-shift.

"ns16550a" is left in the compatible specification since it does work
as long as the bootloader configures the SoC UART power management
registers.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add VPIF node and pins to da850 SoC.  VPIF has two input channels which
can be described using the standard DT ports and endpoints.
Signed-off-by: NKevin Hilman <khilman@baylibre.com>
[nsekhar@ti.com: drop stray newline, typo fixes in commit message]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add the usb1 device node for the da850 soc.
This will allow boards to use the usb1 port
when booting through DT.
Signed-off-by: NAxel Haslam <ahaslam@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

At maximum CPU frequency of 300 MHz the maximum pixel clock frequency
is 37.5 MHz[1]. We must filter out any mode for which the calculated
pixel clock rate would exceed this value.

Specify the max-pixelclock property for the display node for
da850-lcdk.

[1] http://www.ti.com/lit/ds/symlink/am1808.pdf
(SPRS653E, revised March 2014, table 6-110)
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: commit message update]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The tilcdc node name is 'display' as per the ePAPR 1.1 recommendation.
The label is also 'display', but change it to 'lcdc' to make it clear
what the underlying hardware is.
Reviewed-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The mmc controller in da850 supports high speed modes
so add cap-sd-highspeed and cap-mmc-highspeed.
Signed-off-by: NAxel Haslam <ahaslam@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This SoC has a separate pin controller for configuring pullup/pulldown
bias on groups of pins.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Currently the memory controller and master priorities drivers are
enabled in da850.dtsi. For boards for which there are no settings
defined, this makes these drivers emit error messages.

Disable the nodes in da850.dtsi and only enable them for da850-lcdk -
the only board that currently needs them.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This adds the device tree node for the usb otg
controller present in the da850 family of SoC's.
Signed-off-by: NAlexandre Bailon <abailon@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add the nodes for the MSTPRI configuration and DDR2/mDDR memory
controller drivers to da850.dtsi.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while
pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the
driver changes as the driver supports also the legacy binding without
#pinctrl-cells.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add a syscon node for the SoC CFGCHIPn registers. It includes a child node
for the USB PHY that is part of this range of registers.
Signed-off-by: NDavid Lechner <david@lechnology.com>
[nsekhar@ti.com: drop OF_DEV_AUXDATA() addition]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add the bindings for DMA on SPI0
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add pins used by the LCD controller and a disabled LCDC node to be
reused in device trees including da850.dtsi.
Signed-off-by: NKarl Beldan <kbeldan@baylibre.com>
[Bartosz:
  - added the commit description
  - changed the dt node name to a generic one
  - added a da850-specific compatible string
  - removed the tilcdc,panel node
  - moved the pins definitions to da850.dtsi as suggested by
    Sekhar Nori (was in: da850-lcdk.dts)]
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: fix compatible property and remove interrupt-parent]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Currently the davinci da8xx boards use the mach-davinci aemif code.
Instantiating an aemif node into the DT allows to use the ti-aemif
memory driver and is another step to better DT support.
This change adds an aemif node in the dtsi while retiring the nand_cs3
node. The NAND is now instantiated in the dts as a subnode of the aemif
one along with its pins.
Signed-off-by: NKarl Beldan <kbeldan@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This adds 2 pinctrl groups (rtscts, rxtx) for each of the 3 UARTs.
Signed-off-by: NKarl Beldan <kbeldan@baylibre.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

For some devices, the PWMSS is a parent of eCAP and ePWM and provides
the functional clocks for those submodules. The ti,am33xx-ecap and
ti,am33xx-ehrpwm bindings were based on this parent child relationship
where the functional clock would be grabbed from the module's parent.

However, DA850 doesn't have a PWMSS and the eCAP and ePWM provides
their functional clock themselves. Therefore, prefer the new binding
that doesn't assume this parent child relationship.
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
[nsekhar@ti.com: minor commit message fixes]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Fix off by one error in da850 device tree in
the number of INTC interrupts.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
[nsekhar@ti.com: commit message update]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Disable mdio and eth0 in da850.dtsi file. All other
devices are disabled by default and not all boards
will use these devices, so these should be disabled too.

da850-evm.dtb already had status = "okay" for these devices.
da850-enbw-cmc.dts did not, so they were added.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
[nsekhar@ti.com: commit description updates]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add device node and pinmux for SoC spi0.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

da850 has two I2C controllers, but the node for i2c1 was missing.
Add node for i2c1 controller and i2c1 pinmux pins.
Signed-off-by: NPetr Kulhavy <petr@barix.com>
[nsekhar@ti.com: fix indentation]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

TI has been using the physical address in DT after the @ in device nodes.
The device tree convention is to use the same address that is used for
the reg property. This updates all davinci DT files to use the proper
convention.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The gpio node is missing the mandatory property #gpio-cells, which is
causing runtime errors when using GPIOs e.g. with gpio-leds or gpio-keys:

"could not get #gpio-cells for /soc/gpio@1e26000"

This fixes the problem and adds the missing parameter.
The value is 2 according to the gpio-davinci.txt binding.
Signed-off-by: NPetr Kulhavy <petr@barix.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

When possible generic node names should be used. So change the node name
from ehrpwm to pwm.
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the needed bindings so the SPI driver can use DMA with SPI1.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: NSushaanth Srirangapathi <sushaanth.s@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

da850 has two MMC controller, MMCSD1 is served by eDMA1
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: NSushaanth Srirangapathi <sushaanth.s@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add the needed bindings for MMC0 in order to be able to utilize the DMA
instead of PIO mode.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: NSushaanth Srirangapathi <sushaanth.s@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The eDMA1 in da850 has only one TPTC and for example MMC1 is HW events are
handled by it.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: NSushaanth Srirangapathi <sushaanth.s@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3.
With the new bindings boards can customize and tweak the DMA channel
priority to match their needs. With the new binding the memcpy is safe
to be used since with the old binding it was not possible for a driver
to know which channel is allowed to be used as non HW triggered channel.
Using the new binding will allow us to reserve PaRAM slots to be used by
the DSP which was not possible before and prevented the da850 boards to be
moved to DT only.

Note that the DMA memcpy is disabled, it can be enabled by reserving
channels for memcpy by adding the following property to the edma node:
ti,edma-memcpy-channels = <20 21>; /* Reserving channel 20 and 21 for memcpy */
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: NSushaanth Srirangapathi <sushaanth.s@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The size of the eDMA0 CC register space is 0x8000 and not 0x10000.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: NSushaanth Srirangapathi <sushaanth.s@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Node for mcasp0
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>