1. 10 7月, 2011 1 次提交
    • S
      OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed · 93cac2ad
      Santosh Shilimkar 提交于
      On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by
      L3 interconnect. Because of CPU speculative nature, such accesses are
      possible which can lead to indirect access to GPMC and if it's clock is
      not running, it can result in hang/abort on the platform.
      
      Above makes access to GPMC unpredictable during the execution, so it's
      module mode needs to be kept under hardware control instead of software
      control.
      Since the auto gating is supported for GPMC, there isn't any power impact
      because of this change.
      
      The issue was un-covered with security middleware running along with HLOS.
      In this case GPMC had a valid MMU descriptor on secure side where as HLOS
      didn't map the GMPC because it isn't being used.
      Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      [b-cousson@ti.com: Update subject and fix typos in the changelog]
      Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      93cac2ad
  2. 01 6月, 2011 14 次提交
  3. 31 5月, 2011 3 次提交
  4. 27 5月, 2011 1 次提交
  5. 23 5月, 2011 1 次提交
  6. 20 5月, 2011 6 次提交
  7. 18 5月, 2011 4 次提交
  8. 17 5月, 2011 4 次提交
  9. 16 5月, 2011 1 次提交
    • T
      arm: omap2/3: Use generic irq chip · 667a11fa
      Tony Lindgren 提交于
      Use generic irq chip for omap2 & 3.
      
      Note that this patch also leaves out the spurious IRQ warning
      for omap3.
      
      This warning should no longer be needed as the interrupt handlers
      for various devices have implemented the necessayr read-back of
      the posted write.
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      667a11fa
  10. 13 5月, 2011 1 次提交
  11. 12 5月, 2011 1 次提交
  12. 11 5月, 2011 3 次提交