1. 02 6月, 2018 1 次提交
  2. 24 5月, 2018 3 次提交
  3. 08 5月, 2018 2 次提交
    • B
      PCI: pciehp: Add quirk for Command Completed errata · d22b3621
      Bjorn Helgaas 提交于
      Several PCIe hotplug controllers have errata that mean they do not set the
      Command Completed bit unless writes to the Slot Command register change
      "Control" bits.  Command Completed is never set for writes that only change
      software notification "Enable" bits.  This results in timeouts like this:
      
        pciehp 0000:00:1c.0:pcie004: Timeout on hotplug command 0x1038 (issued 65284 msec ago)
      
      When this erratum is present, avoid these timeouts by marking commands
      "completed" immediately unless they change the "Control" bits.
      
      Here's the text of the Intel erratum CF118.  We assume this applies to all
      Intel parts:
      
        CF118        PCIe Slot Status Register Command Completed bit not always
                     updated on any configuration write to the Slot Control
                     Register
      
        Problem:     For PCIe root ports (devices 0 - 10) supporting hot-plug,
                     the Slot Status Register (offset AAh) Command Completed
                     (bit[4]) status is updated under the following condition:
                     IOH will set Command Completed bit after delivering the new
                     commands written in the Slot Controller register (offset
                     A8h) to VPP. The IOH detects new commands written in Slot
                     Control register by checking the change of value for Power
                     Controller Control (bit[10]), Power Indicator Control
                     (bits[9:8]), Attention Indicator Control (bits[7:6]), or
                     Electromechanical Interlock Control (bit[11]) fields. Any
                     other configuration writes to the Slot Control register
                     without changing the values of these fields will not cause
                     Command Completed bit to be set.
      
                     The PCIe Base Specification Revision 2.0 or later describes
                     the “Slot Control Register” in section 7.8.10, as follows
                     (Reference section 7.8.10, Slot Control Register, Offset
                     18h). In hot-plug capable Downstream Ports, a write to the
                     Slot Control register must cause a hot-plug command to be
                     generated (see Section 6.7.3.2 for details on hot-plug
                     commands). A write to the Slot Control register in a
                     Downstream Port that is not hotplug capable must not cause a
                     hot-plug command to be executed.
      
                     The PCIe Spec intended that every write to the Slot Control
                     Register is a command and expected a command complete status
                     to abstract the VPP implementation specific nuances from the
                     OS software. IOH PCIe Slot Control Register implementation
                     is not fully conforming to the PCIe Specification in this
                     respect.
      
        Implication: Software checking on the Command Completed status after
                     writing to the Slot Control register may time out.
      
        Workaround:  Software can read the Slot Control register and compare the
                     existing and new values to determine if it should check the
                     Command Completed status after writing to the Slot Control
                     register.
      
      Per Sinan, the Qualcomm QDF2400 controller also does not set the Command
      Completed bit unless writes to the Slot Command register change "Control"
      bits.
      
      Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
      Link: https://lkml.kernel.org/r/8770820b-85a0-172b-7230-3a44524e6c9f@molgen.mpg.de
      Reported-by: Paul Menzel <pmenzel+linux-pci@molgen.mpg.de>	# Lenovo X60
      Tested-by: Paul Menzel <pmenzel+linux-pci@molgen.mpg.de>	# Lenovo X60
      Signed-off-by: Sinan Kaya <okaya@codeaurora.org>		# Qcom quirk
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      d22b3621
    • B
      PCI: Add Qualcomm vendor ID · 333c8c12
      Bjorn Helgaas 提交于
      Add the Qualcomm vendor ID to pci_ids.h and use it in quirks.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      333c8c12
  4. 21 4月, 2018 1 次提交
  5. 13 4月, 2018 8 次提交
  6. 12 4月, 2018 25 次提交