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  1. 10 2月, 2017 1 次提交
  3. 22 8月, 2016 1 次提交
  5. 15 8月, 2016 1 次提交
    • C
      i2c: at91: fix support of the "alternative command" feature · 434f14e7
      由 Cyrille Pitchen 提交于 
      The "alternative command" feature was introduced with sama5d2 SoCs.

Its purpose is to let the hardware i2c controller automatically send the
STOP condition on the i2c bus at the end of a data transfer.
Without this feature, the i2c driver has to write the 'STOP' bit into the
Control Register so the hardware i2c controller is triggered to send the
STOP condition on the bus.

Using the "alternative command" feature requires to set the transfer data
length into the 8bit DATAL field of the Alternative Command Register.
Hence only data transfers up to 255 bytes can take advantage of the
"alternative command" feature. For greater data transfer sizes, the driver
should use the previous implementation, when the "alternative command"
support was not implemented yet.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      434f14e7
  7. 27 5月, 2016 1 次提交
  9. 04 12月, 2015 1 次提交
  11. 26 10月, 2015 1 次提交
  13. 22 10月, 2015 1 次提交
    • C
      i2c: at91: fix write transfers by clearing pending interrupt first · 6f6ddbb0
      由 Cyrille Pitchen 提交于 
      In some cases a NACK interrupt may be pending in the Status Register (SR)
as a result of a previous transfer. However at91_do_twi_transfer() did not
read the SR to clear pending interruptions before starting a new transfer.
Hence a NACK interrupt rose as soon as it was enabled again at the I2C
controller level, resulting in a wrong sequence of operations and strange
patterns of behaviour on the I2C bus, such as a clock stretch followed by
a restart of the transfer.

This first issue occurred with both DMA and PIO write transfers.

Also when a NACK error was detected during a PIO write transfer, the
interrupt handler used to wrongly start a new transfer by writing into the
Transmit Holding Register (THR). Then the I2C slave was likely to reply
with a second NACK.

This second issue is fixed in atmel_twi_interrupt() by handling the TXRDY
status bit only if both the TXCOMP and NACK status bits are cleared.

Tested with a at24 eeprom on sama5d36ek board running a linux-4.1-at91
kernel image. Adapted to linux-next.
Reported-by: NPeter Rosin <peda@lysator.liu.se>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Tested-by: NPeter Rosin <peda@lysator.liu.se>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Fixes: 93563a6a ("i2c: at91: fix a race condition when using the DMA controller")
Cc: stable@vger.kernel.org #4.1
      6f6ddbb0
  15. 11 6月, 2015 1 次提交
  17. 10 6月, 2015 5 次提交
    • C
      i2c: at91: add support to FIFOs · 5e3cfc6c
      由 Cyrille Pitchen 提交于 
      When FIFOs are available and enabled, the driver now configures the Atmel
eXtended DMA Controller to perform word accesses instead of byte accesses
when possible.
The actual access width depends on the size of the buffer to transmit.

To enable FIFO support the "atmel,fifo-size" property must be set properly
in the I2C controller node of the device tree.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      5e3cfc6c
    • C
      i2c: at91: print hardware version · 6ce461ea
      由 Cyrille Pitchen 提交于 
      The probe() function now prints the hardware version of the I2C
controller.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
[wsa: s/version/hw version/] for clarity]
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      6ce461ea
    • C
      i2c: at91: add support for new alternative command mode · 0ef6f321
      由 Cyrille Pitchen 提交于 
      The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.

This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.

Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.

In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.

Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.

For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      0ef6f321
    • C
      i2c: at91: use BIT() macro to define register bits · e84cf8f0
      由 Cyrille Pitchen 提交于 
      This patch just fixes typo before applying later patches which will use
register bits with index above 16.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      e84cf8f0
    • C
      i2c: at91: fix a race condition when using the DMA controller · 93563a6a
      由 Cyrille Pitchen 提交于 
      For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.

In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);

the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().

Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.

For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      93563a6a
  19. 15 3月, 2015 1 次提交
  21. 13 3月, 2015 1 次提交
  23. 24 11月, 2014 1 次提交
  25. 22 11月, 2014 1 次提交
  27. 12 11月, 2014 1 次提交
  29. 10 11月, 2014 2 次提交
  31. 08 11月, 2014 1 次提交
  33. 20 10月, 2014 1 次提交
  35. 02 9月, 2014 2 次提交
    • M
      i2c: at91: add bound checking on SMBus block length bytes · 75b81f33
      由 Marek Roszko 提交于 
      The driver was not bound checking the received length byte to ensure it was within the
the buffer size that is allocated for SMBus blocks. This resulted in buffer overflows
whenever an invalid length byte was received.
It also failed to ensure the length byte was not zero. If it received zero, it would end up
in an infinite loop as the at91_twi_read_next_byte function returned immediately without
allowing RHR to be read to clear the RXRDY interrupt.

Tested agaisnt a SMBus compliant battery.
Signed-off-by: NMarek Roszko <mark.roszko@gmail.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org
      75b81f33
    • S
      i2c: at91: Fix a race condition during signal handling in at91_do_twi_xfer. · 6721f28a
      由 Simon Lindgren 提交于 
      There is a race condition in at91_do_twi_xfer when signals arrive.
If a signal is recieved while waiting for a transfer to complete
wait_for_completion_interruptible_timeout() will return -ERESTARTSYS.
This is not handled correctly resulting in interrupts still being
enabled and a transfer being in flight when we return.

Symptoms include a range of oopses and bus lockups. Oopses can happen
when the transfer completes because the interrupt handler will corrupt
the stack. If a new transfer is started before the interrupt fires
the controller will start a new transfer in the middle of the old one,
resulting in confused slaves and a locked bus.

To avoid this, use wait_for_completion_io_timeout instead so that we
don't have to deal with gracefully shutting down the transfer and
disabling the interrupts.
Signed-off-by: NSimon Lindgren <simon@aqwary.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org
      6721f28a
  37. 02 8月, 2014 1 次提交
  39. 17 7月, 2014 1 次提交
    • W
      i2c: i2c-at91: Drop class based scanning to improve bootup time · b850579a
      由 Wolfram Sang 提交于 
      This driver has been flagged to drop class based instantiation. The removal
improves boot-up time and is unneeded for embedded controllers. Users have been
warned to switch for some time now, so we can actually do the removal. Keep the
DEPRECATED flag, so the core can inform users that the behaviour finally
changed now. After another transition period, this flag can go, too.
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      b850579a
  41. 12 3月, 2014 1 次提交
  43. 06 3月, 2014 1 次提交
  45. 16 1月, 2014 1 次提交
  47. 15 11月, 2013 1 次提交
  49. 23 8月, 2013 1 次提交
    • W
      i2c: move OF helpers into the core · 687b81d0
      由 Wolfram Sang 提交于 
      I2C of helpers used to live in of_i2c.c but experience (from SPI) shows
that it is much cleaner to have this in the core. This also removes a
circular dependency between the helpers and the core, and so we can
finally register child nodes in the core instead of doing this manually
in each driver. So, fix the drivers and documentation, too.
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      687b81d0
  51. 16 4月, 2013 1 次提交
  53. 02 4月, 2013 1 次提交
  55. 29 3月, 2013 1 次提交
  57. 11 2月, 2013 1 次提交
  59. 28 1月, 2013 1 次提交
  61. 25 1月, 2013 1 次提交
  63. 23 12月, 2012 1 次提交
  65. 25 11月, 2012 2 次提交