- 22 8月, 2011 1 次提交
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由 Nicolas Pitre 提交于
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 04 3月, 2011 1 次提交
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由 Lennert Buytenhek 提交于
This patch makes the various mach dirs that use the plat-orion time code pass in timer and bridge addresses explicitly, instead of having plat-orion get those values by including a mach dir include file -- the latter mechanism is problematic if you want to support multiple ARM platforms in the same kernel image. Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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- 20 10月, 2010 1 次提交
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由 Nicolas Pitre 提交于
Since we're now using addruart to establish the debug mapping, we can remove the io_pg_offst and phys_io members of struct machine_desc. The various declarations were removed using the following script: grep -rl MACHINE_START arch/arm | xargs \ sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }' [ Initial patch was from Jeremy Kerr, example script from Russell King ] Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Eric Miao <eric.miao at canonical.com>
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- 17 7月, 2010 2 次提交
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由 Saeed Bishara 提交于
This patch extends the kirkwood's PCIe support up to 2 controllers as in the 6282 devices. Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Saeed Bishara 提交于
In case the board is configured to boot from spi flash, the mpps will not be configured to select the NAND I/Os. This patch makes sure to select the NAND I/O's regardless to the boot device type. Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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- 09 6月, 2009 1 次提交
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由 Nicolas Pitre 提交于
Common resource and platform device structures are moved to common.c and only the partition table and chip delay remains a per board parameter. Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 27 2月, 2009 4 次提交
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由 Nicolas Pitre 提交于
The RTC and the two XOR engines are internal to the chip, and therefore always available since they don't depend on a particular board layout. Signed-off-by: NNicolas Pitre <nico@marvell.com>
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由 Nicolas Pitre 提交于
Signed-off-by: NNicolas Pitre <nico@marvell.com>
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由 Nicolas Pitre 提交于
Signed-off-by: NNicolas Pitre <nico@marvell.com>
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由 Nicolas Pitre 提交于
Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 26 9月, 2008 1 次提交
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由 Ronen Shitrit 提交于
Remove uart1 init calls for boards that use the physical pins onto which the UART1 signals are multiplexed for different purposes. Signed-off-by: NRonen Shitrit <rshitrit@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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- 05 9月, 2008 1 次提交
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由 Lennert Buytenhek 提交于
Currently, there are two different fields in the mv643xx_eth_platform_data struct that together describe the PHY address -- one field (phy_addr) has the address of the PHY, but if that address is zero, a second field (force_phy_addr) needs to be set to distinguish the actual address zero from a zero due to not having filled in the PHY address explicitly (which should mean 'use the default PHY address'). If we are a bit smarter about the encoding of the phy_addr field, we can avoid the need for a second field -- this patch does that. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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- 07 8月, 2008 1 次提交
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由 Russell King 提交于
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 23 6月, 2008 1 次提交
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由 Saeed Bishara 提交于
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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