Required for dpm on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This makes it easier the understand what the code is
doing.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only Cape Verde supports power gating.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These are needed for certain UVD power saving features.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This is required for certain power management features.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

TN has some additional powergating features beyond what is
supported on ON/LN.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enables PCIE ASPM (Active State Power Management) on
SI asics.

v2: fix typo
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enables PCIE ASPM (Active State Power Management) on
evergreen-cayman asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for accessing certain pcie related registers.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If both the motherboard and GPU support pcie gen2 or 3,
enable it.  PCIE gen2 and 3 offer more bandwidth than
pcie gen1.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SI uses a new atom table revision.  Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SI uses a new atom table.  Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There's a new table for calculating the memory pll
parameters on SI.  Required for SI DPM support.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These functions use acpi methods to adjust the pcie
gen speed.  Used by DPM.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use the new asic callback instead.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Now that the proper fix has been implemented I can
remove the last remnants of the initial implementation.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This properly implemented dynamic state adjustment by
using a working copy of the requested and current
power states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This properly implemented dynamic state adjustment by
using a working copy of the requested and current
power states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This properly implemented dynamic state adjustment by
using a working copy of the requested and current
power states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This properly implemented dynamic state adjustment by
using a working copy of the requested and current
power states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For r6xx-evergreen, they are no-ops as they don't support
any dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for cayman asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching (requires additional acpi support)
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

v2: fold in tdp fix
v3: fix indentation
v4: fix 64 bit div
v5: attempt to fix state enable
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>

Use a dedicated copy of the current power state since
we may have to adjust it on the fly.

v2: fix up redundant state sets
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use a dedicated copy of the current power state since
we may have to adjust it on the fly.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use a dedicated copy of the current power state since
we may have to adjust it on the fly.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Driver needs this information to validate power states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This data will be needed for dpm on newer asics.

v2: fix typo in rebase
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>