1. 26 6月, 2009 1 次提交
  2. 22 4月, 2009 1 次提交
  3. 03 1月, 2008 2 次提交
  4. 28 12月, 2007 2 次提交
    • O
      [POWERPC] pasemi: Distribute interrupts evenly across cpus · d87bf3be
      Olof Johansson 提交于
      By default the OpenPIC on PWRficient will bias to one core (since that
      will improve changes of the other core being able to stay idle/powered
      down). However, this conflicts with most irq load balancing schemes,
      since setting an interrupt to be delivered to either core doesn't really
      result in the load being shared. It also doesn't work well with the
      soft irq disable feature of PPC, since EE will stay on until the first
      interrupt is taken while soft disabled.
      
      Set the gconf0 config bit that enables even distribution of interrupts
      among the two cores.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      d87bf3be
    • O
      [POWERPC] pasemi: Implement NMI support · f365355e
      Olof Johansson 提交于
      Some PWRficient-based boards have a NMI button that's wired up to a GPIO
      as interrupt source. By configuring the openpic accordingly, these get
      delivered as a machine check with high priority, instead of as an external
      interrupt.
      
      The device tree contains a property "nmi-source" in the openpic node
      for these systems, and it's the (hwirq) source for the input.
      
      Also, for these interrupts, the IACK is read from another register than
      the regular (MCACK instead), but they are EOI'd as usual. So implement
      said function for the mpic driver.
      
      Finally, move a couple of external function defines to include/ instead
      of local under sysdev. Being able to mask/unmask and eoi directly saves
      us from setting up a dummy irq handler that will never be called.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      f365355e
  5. 20 12月, 2007 1 次提交
    • O
      [POWERPC] pasemi: Implement MSI support · 38958dd9
      Olof Johansson 提交于
      Implement MSI support for PA Semi PWRficient platforms. MSI is done
      through a special range of sources on the openpic controller, and they're
      unfortunately breaking the usual concepts of how sources are programmed:
      
      * The source is calculated as 512 + the value written into the MSI
        register
      * The vector for this source is added to the source and reported
        through IACK
      
      This means that for simplicity, it makes much more sense to just set the
      vector to 0 for the source, since that's really the vector we expect to
      see from IACK.
      
      Also, the affinity/priority registers will affect 16 sources at a
      time. To avoid most (simple) users from being limited by this, allocate
      16 sources per device but use only one. This means that there's a total
      of 32 sources.
      
      If we get usage scenarions that need more sources, the allocator should
      probably be revised to take an alignment argument and size, not just do
      natural alignment.
      
      Finally, since I'm already touching the MPIC names on pasemi, rename
      the base one from the somewhat odd " PAS-OPIC  " to "PASEMI-OPIC".
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      38958dd9
  6. 11 12月, 2007 1 次提交
  7. 06 12月, 2007 1 次提交
  8. 02 12月, 2007 1 次提交
  9. 30 11月, 2007 1 次提交
  10. 20 11月, 2007 1 次提交
  11. 17 10月, 2007 1 次提交
  12. 13 9月, 2007 2 次提交
  13. 22 8月, 2007 1 次提交
  14. 10 7月, 2007 1 次提交
  15. 08 5月, 2007 1 次提交
  16. 07 5月, 2007 1 次提交
  17. 02 5月, 2007 1 次提交
  18. 27 4月, 2007 2 次提交
  19. 24 4月, 2007 2 次提交
  20. 13 4月, 2007 2 次提交
  21. 07 2月, 2007 7 次提交
  22. 09 1月, 2007 1 次提交
  23. 04 12月, 2006 2 次提交
    • B
      [POWERPC] Refactor 64 bits DMA operations · 12d04eef
      Benjamin Herrenschmidt 提交于
      This patch completely refactors DMA operations for 64 bits powerpc. 32 bits
      is untouched for now.
      
      We use the new dev_archdata structure to add the dma operations pointer
      and associated data to struct device. While at it, we also add the OF node
      pointer and numa node. In the future, we might want to look into merging
      that with pci_dn as well.
      
      The old vio, pci-iommu and pci-direct DMA ops are gone. They are now replaced
      by a set of generic iommu and direct DMA ops (non PCI specific) that can be
      used by bus types. The toplevel implementation is now inline.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      12d04eef
    • B
      [POWERPC] Make pci_read_irq_line the default · f90bb153
      Benjamin Herrenschmidt 提交于
      This patch reworks the way IRQs are fixed up on PCI for arch powerpc.
      
      It makes pci_read_irq_line() called by default in the PCI code for
      devices that are probed, and add an optional per-device fixup in
      ppc_md for platforms that really need to correct what they obtain
      from pci_read_irq_line().
      
      It also removes ppc_md.irq_bus_setup which was only used by pSeries
      and should not be needed anymore.
      
      I've also removed the pSeries s7a workaround as it can't work with
      the current interrupt code anyway. I'm trying to get one of these
      machines working so I can test a proper fix for that problem.
      
      I also haven't updated the old-style fixup code from 85xx_cds.c
      because it's actually buggy :) It assigns pci_dev->irq hard coded
      numbers which is no good with the new IRQ mapping code. It should
      at least use irq_create_mapping(NULL, hard_coded_number); and possibly
      also set_irq_type() to set them as level low.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      f90bb153
  24. 04 10月, 2006 1 次提交
  25. 13 9月, 2006 1 次提交