Certain features need to be enabled after ring tests
(e.g., powergating, etc.).  Add a function pointer
to split out late enable features.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No need to check rdev->pm.num_power_states; this is a vestige
of the old pm code.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Since commit ec39f64b ("drm/radeon/dpm: Convert to use
devm_hwmon_register_with_groups") radeon_hwmon_init() is using
hwmon_device_register_with_groups(), which sets `rdev' as a device
private driver_data, while hwmon_attributes_visible() and
radeon_hwmon_show_temp_thresh() are still waiting for `drm_device'.

Fix them by using dev_get_drvdata(), in order to avoid this oops:

  BUG: unable to handle kernel paging request at 0000000000001e28
  IP: [<ffffffffa02ae8b4>] hwmon_attributes_visible+0x18/0x3d [radeon]
  PGD 15057e067 PUD 151a8e067 PMD 0
  Oops: 0000 [#1] PREEMPT SMP
  Call Trace:
    internal_create_group+0x114/0x1d9
    sysfs_create_group+0xe/0x10
    sysfs_create_groups+0x22/0x5f
    device_add+0x34f/0x501
    device_register+0x15/0x18
    hwmon_device_register_with_groups+0xb5/0xed
    radeon_hwmon_init+0x56/0x7c [radeon]
    radeon_pm_init+0x134/0x7e5 [radeon]
    radeon_modeset_init+0x75f/0x8ed [radeon]
    radeon_driver_load_kms+0xc6/0x187 [radeon]
    drm_dev_register+0xf9/0x1b4 [drm]
    drm_get_pci_dev+0x98/0x129 [drm]
    radeon_pci_probe+0xa3/0xac [radeon]
    pci_device_probe+0x6e/0xcf
    driver_probe_device+0x98/0x1c4
    __driver_attach+0x5c/0x7e
    bus_for_each_dev+0x7b/0x85
    driver_attach+0x19/0x1b
    bus_add_driver+0x104/0x1ce
    driver_register+0x89/0xc5
    __pci_register_driver+0x58/0x5b
    drm_pci_init+0x86/0xea [drm]
    radeon_init+0x97/0x1000 [radeon]
    do_one_initcall+0x7f/0x117
    load_module+0x1583/0x1bb4
    SyS_init_module+0xa0/0xaf
Signed-off-by: NSergey Senozhatsky <sergey.senozhatsky@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Simplify the code and fix race condition seen because
attribute files were created after hwmon device registration.
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

After adjusting the dpm parameters this seems to be
stable on most TN systems.  DPM is important for APUs
since the boot clocks are generally pretty low.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This updates the CI dpm (dynamic power management)
support for hawaii.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Move the ktime_get() clock readouts and potential preempt_disable()
calls from drm core into kms driver to make it compatible with the
api changes in the drm core.

This should not introduce any change in functionality or behaviour
in radeon-kms, just a reshuffling of code.
Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

If the user has forced the state high or low, retain that preference
even when we switch power states.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=70654Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If the thermal state is active, we are in the lowest performance level
to cool down the chip.  Don't let the user force it higher.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Seems to be stable on them.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Seems to be stable on them.  There are still some issues
with the performance states staying in the highest levels
on certain cards when multiple monitors are attached, but
being that the the cards are always in their highest power
state at boot up anyway, this doesn't really change anything
and improves things in all other cases.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Seems to be stable on them.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Seems to be stable on them and improves peformance
as most SI asics have very low boot clocks.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DPM seems to be stable on these asics and it drastically
improves performance depending on the boot clocks.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Avoids spamming the system log for chips where dpm is enabled by
default, but prints then messages when users force it on for other
asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Always use the regular UVD state for now.  This fixes
a performance regression with UVD playback on certain APUs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This is a partial revert of c6cf7777.

We need to take into account the clk voltage dependencies of the
board.  Not doing so can lead to stability issues on certain
boards if the clks exceed the levels in the dep tables.

DPM already takes that into account, so for optimal performance,
use DPM.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Calling force_performance_level() from set_power_state()
doesn't work on some asics because the current power
state pointer has not been properly updated at that point.
Move the calls to force_performance_level() out of the
asic specific set_power_state() functions and into
the main power state sequence.

Fixes dpm resume on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

bapm is a pm feature for sharing the power budget between
the GPU and the CPU on APUs.  It needs to be enabled or
disabled in certain circumstances.  For now, disable it
when on battery and enable it when on AC power.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The hwmon sysfs interface allows exposing temperature limits. The "max"
and "min" thresholds will be exposed as a critical high limit and its
hysteresis value, respectively. This gives the user a better idea of how
well cooling is doing and whether it is sufficient.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: David Airlie <airlied@linux.ie>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

You can get the driver data from struct device directly, there's no
need to get the PCI device first.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: David Airlie <airlied@linux.ie>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Starting on CIK, multi-media blocks like UVD no longer
have special power state.  Rather they have their own
DPM implementation which adjusts their clocks dynamically
when active.  When they are not active, the blocks are
powergated to save power.

v2: add missing pm locks
v3: rebase on uvd state selection rework
v4: fix inverted logic typo noticed by Christian
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for KB/KV asics.  This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This added support for the on-chip thermal sensors on
CIK asics.

v2: fix register offset.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Newer asics don't have specific UVD states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use the UVD handle information to determine which
which power states to select when using UVD.  For
example, decoding a single SD stream requires much
lower clocks than multiple HD streams.

v2: switch to a cleaner dpm/uvd interface
v3: change the uvd power state while streams
are active if need be
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The smc ucode is required for dpm (dynamic power
management), but if it's missing just skip dpm setup
and don't disable acceleration.

Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=67876Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The rlc is required for dpm to work properly, so if
the rlc ucode is missing, don't enable dpm.  Enabling
dpm without the rlc enabled can result in hangs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If the vblank time is too short to adjust mclk,
assume multiple displays (no mclk adjustments).
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Looks like a remnant from an old rebase.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows you to force specific power levels within a power
state.  Due to hardware restrictions between generations, the
interface is limited to the following 3 selections:

auto: all levels enabled
low: forced to the lowest power level
high: forced to the highest power level
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state.  The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected.  This change
switches to the "balanced" profile by default which ends up being
the internal performance profile.  When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.

For most asics this changes nothing.  For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For chips without debugfs dpm support say that it's not
implemented rather than not supported to avoid confusion
about DPM support in general.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This lays the frameworks to report realtime power level
feedback.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for SI asics.  This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Now that the proper fix has been implemented I can
remove the last remnants of the initial implementation.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed to properly handle dynamic state adjustment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>