1. 07 8月, 2013 2 次提交
    • C
      tile PCI RC: support more MSI-X interrupt vectors · 90d9dd66
      Chris Metcalf 提交于
      To support PCIe devices with higher number of MSI-X interrupt vectors,
      e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more
      MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more
      vectors in addition to ~10 from the Map Mem regions.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      90d9dd66
    • C
      tile: support LSI MEGARAID SAS HBA hybrid dma_ops · 803c874a
      Chris Metcalf 提交于
      The LSI MEGARAID SAS HBA suffers from the problem where it can do
      64-bit DMA to streaming buffers but not to consistent buffers.
      In other words, 64-bit DMA is used for disk data transfers and 32-bit
      DMA must be used for control message transfers. According to LSI,
      the firmware is not fully functional yet. This change implements a
      kind of hybrid dma_ops to support this.
      
      Note that on most other platforms, the 64-bit DMA addressing space is the
      same as the 32-bit DMA space and they overlap the physical memory space.
      No special arrangement is needed to support this kind of mixed DMA
      capability.  On TILE-Gx, the 64-bit DMA space is completely separate
      from the 32-bit DMA space.  Due to the use of the IOMMU, the 64-bit DMA
      space doesn't overlap the physical memory space.  On the other hand,
      the 32-bit DMA space overlaps the physical memory space under 4GB.
      The separate address spaces make it necessary to have separate dma_ops.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      803c874a
  2. 06 8月, 2013 5 次提交
  3. 02 8月, 2013 2 次提交
  4. 31 7月, 2013 2 次提交
  5. 18 7月, 2013 1 次提交
  6. 13 7月, 2013 3 次提交
  7. 12 7月, 2013 3 次提交
  8. 11 7月, 2013 5 次提交
  9. 10 7月, 2013 17 次提交