- 14 7月, 2014 2 次提交
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由 Heiko Stübner 提交于
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-By: NMax Schwarz <max.schwarz@online.de> Tested-By: NMax Schwarz <max.schwarz@online.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Heiko Stübner 提交于
This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-By: NMax Schwarz <max.schwarz@online.de> Tested-By: NMax Schwarz <max.schwarz@online.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 21 5月, 2014 1 次提交
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由 Rob Herring 提交于
Adding function type checking to CLK_OF_DECLARE found a type mismatch with rk2928_gate_clk_init. The function only takes a single struct device_node parameter. Signed-off-by: NRob Herring <robh@kernel.org> Acked-by: NMike Turquette <mturquette@linaro.org>
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- 21 6月, 2013 1 次提交
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由 Heiko Stübner 提交于
This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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