- 24 11月, 2014 16 次提交
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由 Andrew Bresticker 提交于
There's no reason for the pending and masked interrupt bitmasks to be global. Just declare them on the stack in gic_get_int() since they only consume (256*2)/8 = 64 bytes. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8131/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Sort the #includes and remove those which are unnecessary. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8130/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Remove duplicate #defines and unnecessary #includes, fix parenthesization, and re-order register definitions in ascending order. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8128/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Get rid of the ugly GICREAD/GICWRITE/GICBIS macros and use proper iomem accessors instead. Since the GIC registers are not directly accessed outside of the GIC driver any more, make gic_base static and move all the GIC register manipulation macros out of gic.h, converting them to static inline functions. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8127/ Patchwork: https://patchwork.linux-mips.org/patch/8229/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Export the function gic_get_count_width to read the width of the GIC global counter from GIC_SH_CONFIG. Update the GIC clocksource driver to use this new function. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8124/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Now that all GIC interrupt routing and handling logic is in the GIC driver itself, un-export variables/functions which are no longer used outside the GIC driver. This also allows us to remove gic_compare_int and combine gic_get_int_mask with gic_get_int since these interfaces are no longer used. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7820/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7819/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
GIC edge-triggered interrupts must be acknowledged by clearing the edge detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered irq_chip with the appropriate irq_ack() callback. This also allows us to get rid of gic_irq_flags. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7818/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Instead of requiring platforms to define the correct GIC_NUM_INTRS, use the value reported in GIC_SH_CONFIG. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7817/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7816/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Use a simple IRQ domain for the MIPS GIC. Remove the gic_platform_init callback as it's no longer necessary for it to set the irqchip. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7811/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
If the online CPU check in gic_set_affinity() fails, return a proper errno value instead of -1. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7814/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Implement an irq_set_type callback for the GIC which is used to set the polarity and trigger type of GIC interrupts. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7810/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
There's no need for platforms to have their own GIC irq_ack/irq_eoi callbacks. irq_ack need only clear the GIC's edge detector on edge-triggered interrupts and there's no need at all for irq_eoi. Also get rid of the mask_ack callback since it's not necessary either. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7809/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 02 11月, 2014 2 次提交
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由 Grzegorz Jaszczyk 提交于
In both Armada-375 and Armada-38x MPIC interrupts should be identified by reading cause register multiplied by the interrupt mask. A lack of above mentioned multiplication resulted in a bug, caused by the fact that in Armada-375 and Armada-38x some of the interrupts (e.g. network interrupts) can be handled either as a GIC or MPIC interrupts. Therefore during MPIC interrupts handling, cause register shows hits from interrupts even if they are masked for MPIC but unmasked for a GIC. This resulted in 'bad IRQ' error, because masked MPIC interrupt without registered interrupt handler, was trying to be handled during interrupt handling procedure of some other unmasked MPIC interrupt (e.g. local timer irq). This commit fixes that by ensuring that during MPIC interrupt handling only interrupts that are unmasked for MPIC are processed. Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Fixes: bc69b8ad ("irqchip: armada-370-xp: Setup a chained handler for the MPIC") Cc: <stable@vger.kernel.org> # v3.15+ Acked-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1411643839-64925-3-git-send-email-jaz@semihalf.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Grzegorz Jaszczyk 提交于
The MSI interrupts use the 16 high doorbells, which are notified by using IRQ1 of the main interrupt controller. The MSI interrupts were handled correctly for Armada-XP and Armada-370 but not for Armada-375 and Armada-38x, which use chained handler for the MPIC. This commit fixes that by checking proper interrupt number in chained handler for the MPIC. Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Fixes: bc69b8ad ("irqchip: armada-370-xp: Setup a chained handler for the MPIC") Cc: <stable@vger.kernel.org> # v3.15+ Acked-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1411643839-64925-2-git-send-email-jaz@semihalf.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 02 10月, 2014 1 次提交
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由 Alexander Gordeev 提交于
Move MSI checks from arch_msi_check_device() to arch_setup_msi_irqs(). This makes the code more compact and allows removing arch_msi_check_device() from generic MSI code. Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NAlexander Gordeev <agordeev@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJason Cooper <jason@lakedaemon.net> CC: Thomas Gleixner <tglx@linutronix.de>
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- 26 9月, 2014 1 次提交
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由 Masanari Iida 提交于
This patch fix spelling typos found in Kconfig. Signed-off-by: NMasanari Iida <standby24x7@gmail.com> Acked-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 19 9月, 2014 1 次提交
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由 Christoph Lameter 提交于
The raw_cpu_read() conversion dropped the fetch of the offset from base->percpu_base in gic_get_percpu_base. Signed-off-by: NChristoph Lameter <cl@linux.com> Reported-and-tested-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: NNicolas Pitre <nico@linaro.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NTejun Heo <tj@kernel.org>
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- 17 9月, 2014 8 次提交
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由 Felipe Balbi 提交于
no fuctional changes. Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
maximum number of MIR register is 4, rather than 3. Fix that. Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
When TURBO bit is set in the INTC_IDLE register, the input synchronizer clock will be autogated based on activity on the INTC. Because this idle mode increases the interrupt latency by 2 clock cycles, we're only enabling it during suspend. Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
When PROTECTION bit in enabled in PROTECTION register, INTC's registers are only accessible from privileged mode. Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
of_iomap(), which is called from omap_init_irq_of(), already takes care of making sure we have a valid resource to deal with. Because of that, we can safely remove our explicit call to of_address_to_resource(). Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
no functional changes, just making sure comment follows Coding Style. Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
We already hold the number of Pending registers in omap_nr_pending. Let's use that instead. Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
Just move the code over as it has no dependencies on arch/arm/ anymore. Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 14 9月, 2014 7 次提交
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由 Sudeep Holla 提交于
When a CPU enters a low power state, the contents of the GICv3/4 system registers are lost. They need to be saved and restored if required. For now, since most of the GICv3 register are set some initial values and not modified at runtime, it is better to re-initialise rather than saving and restoring them. It may need to be saved and restored in future if required. This patch adds a notifier to disable the redistributor(if allowed) and Group1 interrupts when powering down the processor and to re-initialise the system registers on wakeup. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NSudeep Holla <sudeep.holla@arm.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1409065415-20176-3-git-send-email-sudeep.holla@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sudeep Holla 提交于
Currently gic_enable_redist configures the redistributors to never assert WakeRequest signal. However when powering down the processors with wake-up enabled(i.e suspend), we need to configure it to assert that signal. This patch extends gic_enable_redist so that the redistributor can be configure to assert WakeRequest and hold interrupts as pending. This is useful in suspending the processors. This patch also adds check to make sure GICR_WAKER is accessible when configuring it. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NSudeep Holla <sudeep.holla@arm.com> [maz: removed reference to GICD_CTLR.DS and added read-back of GICR_WAKER to check that it is not RAZ/WI] Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1409065415-20176-2-git-send-email-sudeep.holla@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Geert Uytterhoeven 提交于
This is just enough to let pm_clk_*() enable the functional clock, and manage it for suspend/resume, if present. Before, it was assumed enabled by the bootloader or reset state. To prevent the clock from being disabled while the module is needed for wake-up, implement irq_chip.irq_set_wake(), which increments/decrements the clock's enable_count when needed. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Link: https://lkml.kernel.org/r/1410527720-18061-3-git-send-email-geert+renesas@glider.beSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Geert Uytterhoeven 提交于
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Link: https://lkml.kernel.org/r/1410527720-18061-2-git-send-email-geert+renesas@glider.beSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Alexandre Belloni 提交于
Add sama5d4 support to irq-atmel-aic5. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Link: https://lkml.kernel.org/r/1410536587-24607-2-git-send-email-alexandre.belloni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Alexandre Belloni 提交于
The FUSE and RAM controllers don't have any connected IRQs, reducing the number of IRQs to 48. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Link: https://lkml.kernel.org/r/1410446511-29477-1-git-send-email-alexandre.belloni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Florian Fainelli 提交于
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using a single enable register. This interrupt controller is always present on the platforms supported by the irq-brcmstb-l2 driver, hence the reason why both are compiled using the same Kconfig symbol. [jac] removed the following warning: drivers/irqchip/irq-bcm7120-l2.c: In function 'bcm7120_l2_intc_irq_handle': drivers/irqchip/irq-bcm7120-l2.c:49:27: warning: unused variable 'gc' [-Wunused-variable] Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1410309862-27784-2-git-send-email-f.fainelli@gmail.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 03 9月, 2014 4 次提交
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由 Marc Zyngier 提交于
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi> Link: https://lkml.kernel.org/r/1409047421-27649-22-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Marc Zyngier 提交于
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Link: https://lkml.kernel.org/r/1409047421-27649-21-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Marc Zyngier 提交于
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Link: https://lkml.kernel.org/r/1409047421-27649-20-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Marc Zyngier 提交于
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1409047421-27649-19-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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