1. 15 7月, 2017 2 次提交
    • S
      drm/edid: complete CEA modedb(VIC 1-107) · 8ec6e075
      Shashank Sharma 提交于
      CEA-861-F specs defines new video modes to be used with
      HDMI 2.0 EDIDs. The VIC range has been extended from 1-64 to
      1-107.
      
      Our existing CEA modedb contains only 64 modes (VIC=1 to VIC=64). Now
      to be able to parse new CEA modes using the existing methods, we have
      to complete the modedb (VIC=65 onwards).
      
      This patch adds:
      - Timings for existing CEA video modes (from VIC=65 till VIC=92)
      - Newly added 4k modes (from VIC=93 to VIC=107).
      
      The patch was originaly discussed and reviewed here:
      https://patchwork.freedesktop.org/patch/135810/
      
      Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
      Cc: Jose Abreu <Jose.Abreu@synopsys.com>
      Cc: Andrzej Hajda <a.hajda@samsung.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Harry Wentland <harry.wentland@amd.com>
      
      V2: Rebase
      V3: Rebase
      V4: Added native bit handling as per CEA-861-F spec (Ville)
      V5: Fix timings for VIC 77:1920x1080 and 104:3840x2160p (Ville)
          Remove unnecessary paranthesis from function svd_to_vic (Ville)
          Added r-b (Neil)
      V6: Rebase
      V7: Fix indentation for modes from VIC 80
      Reviewed-by: NJose Abreu <Jose.Abreu@synopsys.com>
      Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
      Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
      Acked-by: NHarry Wentland <harry.wentland@amd.com>
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1499960000-9232-3-git-send-email-shashank.sharma@intel.com
      [vsyrjala: Fix up remaining formatting/indentation issues]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      8ec6e075
    • S
      drm: handle HDMI 2.0 VICs in AVI info-frames · 0c1f528c
      Shashank Sharma 提交于
      HDMI 1.4b support the CEA video modes as per range of CEA-861-D (VIC 1-64).
      For any other mode, the VIC filed in AVI infoframes should be 0.
      HDMI 2.0 sinks, support video modes range as per CEA-861-F spec, which is
      extended to (VIC 1-107).
      
      This patch adds a bool input variable, which indicates if the connected
      sink is a HDMI 2.0 sink or not. This will make sure that we don't pass a
      HDMI 2.0 VIC to a HDMI 1.4 sink.
      
      This patch touches all drm drivers, who are callers of this function
      drm_hdmi_avi_infoframe_from_display_mode but to make sure there is
      no change in current behavior, is_hdmi2 is kept as false.
      
      In case of I915 driver, this patch:
      - checks if the connected display is HDMI 2.0.
      - HDMI infoframes carry one of this two type of information:
      	- VIC for 4K modes for HDMI 1.4 sinks
      	- S3D information for S3D modes
        As CEA-861-F has already defined VICs for 4K videomodes, this
        patch doesn't allow sending HDMI infoframes for HDMI 2.0 sinks,
        until the mode is 3D.
      
      Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
      Cc: Jose Abreu <jose.abreu@synopsys.com>
      Cc: Andrzej Hajda <a.hajda@samsung.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      
      PS: This patch touches a few lines in few files, which were
      already above 80 char, so checkpatch gives 80 char warning again.
      - gpu/drm/omapdrm/omap_encoder.c
      - gpu/drm/i915/intel_sdvo.c
      
      V2: Rebase, Added r-b from Andrzej
      V3: Addressed review comment from Ville:
      	- Do not send VICs in both AVI-IF and HDMI-IF
      	  send only one of it.
      V4: Rebase
      V5: Added r-b from Neil.
          Addressed review comments from Ville
          - Do not block HDMI vendor IF, instead check for VIC while
            handling AVI infoframes
      V6: Rebase
      V7: Rebase
      Reviewed-by: NAndrzej Hajda <a.hajda@samsung.com>
      Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1499960000-9232-2-git-send-email-shashank.sharma@intel.comSigned-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      0c1f528c
  2. 02 5月, 2017 1 次提交
  3. 21 3月, 2017 3 次提交
  4. 06 3月, 2017 1 次提交
  5. 28 2月, 2017 1 次提交
  6. 21 2月, 2017 2 次提交
  7. 15 2月, 2017 1 次提交
  8. 08 2月, 2017 1 次提交
  9. 02 2月, 2017 1 次提交
  10. 27 1月, 2017 4 次提交
  11. 02 1月, 2017 1 次提交
  12. 18 12月, 2016 1 次提交
  13. 29 11月, 2016 1 次提交
  14. 09 11月, 2016 1 次提交
  15. 08 11月, 2016 1 次提交
  16. 25 10月, 2016 1 次提交
  17. 17 10月, 2016 2 次提交
  18. 04 10月, 2016 8 次提交
  19. 19 8月, 2016 1 次提交
  20. 17 8月, 2016 1 次提交
  21. 09 8月, 2016 2 次提交
    • M
      drm/edid: Set 8 bpc color depth for displays with "DFP 1.x compliant TMDS". · 210a021d
      Mario Kleiner 提交于
      According to E-EDID spec 1.3, table 3.9, a digital video sink with the
      "DFP 1.x compliant TMDS" bit set is "signal compatible with VESA DFP 1.x
      TMDS CRGB, 1 pixel / clock, up to 8 bits / color MSB aligned".
      
      For such displays, the DFP spec 1.0, section 3.10 "EDID support" says:
      
      "If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.)
       without extensions, the host will make the following assumptions:
      
       1. 24-bit MSB-aligned RGB TFT
       2. DE polarity is active high
       3. H and V syncs are active high
       4. Established CRT timings will be used
       5. Dithering will not be enabled on the host"
      
      So if we don't know the bit depth of the display from additional
      colorimetry info we should assume 8 bpc / 24 bpp by default.
      
      This patch adds info->bpc = 8 assignement for that case.
      Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      210a021d
    • M
      drm/edid: Add 6 bpc quirk for display AEO model 0. · e10aec65
      Mario Kleiner 提交于
      Bugzilla https://bugzilla.kernel.org/show_bug.cgi?id=105331
      reports that the "AEO model 0" display is driven with 8 bpc
      without dithering by default, which looks bad because that
      panel is apparently a 6 bpc DP panel with faulty EDID.
      
      A fix for this was made by commit 013dd9e0
      ("drm/i915/dp: fall back to 18 bpp when sink capability is unknown").
      
      That commit triggers new regressions in precision for DP->DVI and
      DP->VGA displays. A patch is out to revert that commit, but it will
      revert video output for the AEO model 0 panel to 8 bpc without
      dithering.
      
      The EDID 1.3 of that panel, as decoded from the xrandr output
      attached to that bugzilla bug report, is somewhat faulty, and beyond
      other problems also sets the "DFP 1.x compliant TMDS" bit, which
      according to DFP spec means to drive the panel with 8 bpc and
      no dithering in absence of other colorimetry information.
      
      Try to make the original bug reporter happy despite the
      faulty EDID by adding a quirk to mark that panel as 6 bpc,
      so 6 bpc output with dithering creates a nice picture.
      
      Tested by injecting the edid from the fdo bug into a DP connector
      via drm_kms_helper.edid_firmware and verifying the 6 bpc + dithering
      is selected.
      
      This patch should be backported to stable.
      Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      e10aec65
  22. 23 5月, 2016 3 次提交