In success case the function bus_find_device_by_name calls
get_device. In our context put_device should be called to
decrease the device count usage.
Signed-off-by: NRoman Tereshonkov <roman.tereshonkov@nokia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h

percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>

omap2_mcspi_transfer() gets called in omap2_mcspi_work() when the
transaction speed_hz or bits_per_word fields are non-zero.

omap2_mcspi_transfer() does not look at the speed_hz field so
the override speed value is ignored.

The code should probably change to one of these options.

1. Skip the call to omap2_mcsp_transfer() if the only reason was a
non-zero speed_hz and it's not going to be used.

2. Use the new speed_hz value provided

The patch below uses the speed_hz value.
Signed-off-by: NScott Ellis <scott@jumpnowtek.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Check spi->controller_state before dereferencing.

Shows up NULL here when using spi_alloc_device()/spi_add_device()
and spi_add_device() fails before spi_setup(). Calling spi_dev_put()
on the leftover spi_device results in the error.
Signed-off-by: NScott Ellis <scott@jumpnowtek.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

DMA can only be done from physical addresses; move the "virt_to_phys"
source/destination buffer address translation from the dbdma queueing
functions (since the hardware can only DMA to/from physical addresses)
to their respective users.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove dbdma compat macros, move remaining users over to default
queueing functions and -flags.

(Queueing function signature has changed in order to give
 a build failure instead of silent functional changes due
 to the no longer implicitly specified DDMA_FLAGS_IE flag)
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Correct SPI clock frequency division factor rounding, preventing clock rates
higher than the maximum specified clock frequency being used.

When specifying spi-max-frequency = <10000000> in the device tree,
the resulting frequency was 11.1 MHz, with spibrg being 133333332.

According to the freescale data sheet [1], the spi clock rate is
spiclk = spibrg / (4 * (pm+1))

The existing code calculated
  pm = mpc8xxx_spi->spibrg / (hz * 4); pm--;
  resulting in pm = (int) (3.3333) - 1 = 2,
  resulting in spiclk = 133333332/(4*(2+1)) = 11111111

  With the fix,
   pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; pm--;
   resulting in pm = (int) (4.3333) - 1 = 3,
   resulting in spiclk = 133333332/(4*(3+1)) = 8333333

   Without the fix, for every desired SPI frequency that
   is not exactly derivable from spibrg, pm will be too
   small due to rounding down, resulting in a too high SPI clock,
   so we need a pm which is one higher.

   For values that are exactly derivable, spibrg will
   be dividable by (hz*4) without remainder, and
   (int) ((spibrg-1)/(hz*4)) will be one lower than
   (int) (spibrg)/(hz*4), which is compensated by adding 1.
   For these values, the fixed version calculates the same pm
   as the unfixed version.

   For all values that are not exactly derivable,
   spibrg will be not dividable by (hz*4) without
   remainder, and (int) ((spibrg-1)/(hz*4)) will be
   the same as (int) (spibrg)/(hz*4), and the calculated pm will
   be one higher than calculated by the unfixed version.

References:
[1] http://www.freescale.com/files/32bit/doc/ref_manual/MPC8315ERM.pdf,
   page 22-10 -> 1398
Signed-off-by: NErnst Schwab <eschwab@online.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Replace ARCH_OMAP34XX with ARCH_OMAP3
Signed-off-by: NTony Lindgren <tony@atomide.com>

Convert ARCH_OMAP24XX to ARCH_OMAP2
Signed-off-by: NTony Lindgren <tony@atomide.com>

In particular, several occurances of funny versions of 'success',
'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address',
'beginning', 'desirable', 'separate' and 'necessary' are fixed.
Signed-off-by: NDaniel Mack <daniel@caiaq.de>
Cc: Joe Perches <joe@perches.com>
Cc: Junio C Hamano <gitster@pobox.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

String constants that are continued on subsequent lines with \
are not good.
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The spi_sh_msiof.c driver presently misconfigures REDG and TEDG. TEDG==0
outputs data at the **rising edge** of the clock and REDG==0 samples data
at the **falling edge** of the clock. Therefore for SPI, TEDG must be
equal to REDG, otherwise the last byte received is not sampled in SPI
mode 3.

This brings the driver in line with the SH7723 HW Reference Manual
settings documented in Figures 20.20 and 20.21 ("SPI Clock and data
timing").
Signed-off-by: NMarkus Pietrek <Markus.Pietrek@emtrion.de>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Added logic to cap TX FIFO fill size based on current free RX
FIFO entries instead of TX status flags. This is to prevent
an issue with RX FIFO overflows.
Signed-off-by: NKevin Wells <kevin.wells@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

dw_spi_mmio is dependent on the clock framework. This marks it as such
in Kconfig.
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Minor code style cleanups following comments by Wolfram Sang
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Adds a memory-mapped I/O dw_spi platform device.
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

So that interface drivers could be built as modules
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This allows the switching between transfer modes between 'transmit only',
'receive only' and 'transmit and receive' modes. Due to the design of the SPI
block, changing transfer modes requires that the block be disabled; in doing
so the chipselect line is inherently deasserted and (usually) the attached
device discards its state. Consequentially, switching modes requires that a
platform-specific chipselect function has been defined so that the chipselect
is not dropped during the change.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The 'poll_transfer' function employs a conditional to test whether the
transmit buffer is valid; in doing so, on a receive operation no data is
clocked out, thus no data is clocked in and ultimately errors appear.

This removes the conditional as the transmit function will be set to a null
writer when the transmit buffer is invalid, allowing the driver to clock
0x00 out to the device to receive data from the device.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

As per the function signature.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

FIFO depth is configurable for each implementation of DW core,
so add a depth detection for those interface drivers who don't set
the fifo_len explicitly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Acked-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Section mismatch in reference from the function dw_spi_add_host()
to the function init_queue()
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

xilinx_spi presently makes some fairly questionable assumptions about I/O
routines, and attempts to assign ioread32/iowrite32 and friends directly
to its own internal function pointers. On many platforms these I/O
routines are macros or wrappers and not actual functions on their own,
resulting in things like:

ERROR: "ioread32be" [drivers/spi/xilinx_spi.ko] undefined!
ERROR: "iowrite32be" [drivers/spi/xilinx_spi.ko] undefined!
ERROR: "iowrite32" [drivers/spi/xilinx_spi.ko] undefined!
ERROR: "ioread32" [drivers/spi/xilinx_spi.ko] undefined!

If xilinx_spi wants to do this sort of casting, it needs to provide its
own wrappers for these, or change how it does accesses completely.

I've opted for the first approach, and the attached silly patch does
that. If someone with the hardware available wants to give the second
option a try that's ok too. In any event, the current code is broken for
at least: arm, avr32, blackfin, microblaze, mn10300, and sh.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NRichard Röjfors <richard.rojfors@pelagicore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Useful when debugging multiple spi channels.
Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Update the MSIOF driver to remove the architecture
speficic spi header file and add err.h. This makes
the driver compile on non-SH architectures.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Now dw_spi core fully supports 3 transfer modes: pure polling,
DMA and IRQ mode. IRQ mode will use the FIFO half empty as
the IRQ trigger, so each interface driver need set the fifo_len,
so that core driver can handle it properly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Make the driver wait at least  for 1 jiffie before issuing the
warning, no matter what HZ is set to
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Since most of the chip-selects are simply going to be like
gpio_set_value, it would do good to have the same callback type
so that it could simply be made to point at gpio_set_value.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Header for platform specific stuff has been rename to include the SoC
type. Include the new header instead.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add precautionary check before releasing memory region.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The pointer to SPI rate source clock had better be the member of
driver local data structure rather than platform specific.
Also, remove definitions of variable 'sci' that are rendered
useless as a consequence.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The instance of SPI clock for controller and that used for generating
signals ought to be independently handled.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Rename 'struct s3c64xx_spi_cntrlr_info' to lesser wordy
'struct s3c64xx_spi_info'
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

platform_get_irq returns -ENXIO on failure, so !irq was probably
always true.  Make irq a signed variable and compare irq <= 0.  Note
that a return value of zero is still handled as error even though this
could mean irq0.

This is a followup to 305b3228 that
changed the return value of platform_get_irq from 0 to -ENXIO on error.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add support for the QSPI controller found some on Freescale/Motorola
Coldfire MCUs.

Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are
supported.  The hardware drives the MISO, MOSI and SCLK lines, but the chip
selects are managed via GPIO and must be configured by the board code.

The QSPI controller has an 80 byte buffer which allows us to transfer up to 16
words at a time.  For transfers longer than 16 words, we split the buffer in
half so we can update in one half while the controller is operating on the
other half.  Interrupt latencies then ultimately limits our sustained thru-put
to something less than half the maximum speed supported by the part.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The match_table field of the struct of_device_id is constant
in <linux/of_platform.h> so it is worth to make the initialization
data constant.

The semantic match that finds this kind of pattern is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r@
disable decl_init,const_decl_init;
identifier I1, I2, x;
@@
	struct I1 {
	  ...
	  const struct I2 *x;
	  ...
	};
@s@
identifier r.I1, y;
identifier r.x, E;
@@
	struct I1 y = {
	  .x = E,
	};
@c@
identifier r.I2;
identifier s.E;
@@
	const struct I2 E[] = ... ;
@depends on !c@
identifier r.I2;
identifier s.E;
@@
+	const
	struct I2 E[] = ...;
// </smpl>
Signed-off-by: NMárton Németh <nm127@freemail.hu>
Cc: Julia Lawall <julia@diku.dk>
Cc: cocci@diku.dk
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>