1. 27 3月, 2011 1 次提交
    • K
      crypto: caam - Add support for the Freescale SEC4/CAAM · 8e8ec596
      Kim Phillips 提交于
      The SEC4 supercedes the SEC2.x/3.x as Freescale's
      Integrated Security Engine.  Its programming model is
      incompatible with all prior versions of the SEC (talitos).
      
      The SEC4 is also known as the Cryptographic Accelerator
      and Assurance Module (CAAM); this driver is named caam.
      
      This initial submission does not include support for Data Path
      mode operation - AEAD descriptors are submitted via the job
      ring interface, while the Queue Interface (QI) is enabled
      for use by others.  Only AEAD algorithms are implemented
      at this time, for use with IPsec.
      
      Many thanks to the Freescale STC team for their contributions
      to this driver.
      Signed-off-by: NSteve Cornelius <sec@pobox.com>
      Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
      Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
      8e8ec596
  2. 23 3月, 2011 1 次提交
  3. 22 3月, 2011 2 次提交
  4. 21 3月, 2011 1 次提交
    • M
      powerpc: Document the Open PIC device tree binding · a99eff39
      Meador Inge 提交于
      This binding documents several properties that have been in use for quite
      some time, and adds one new property 'pic-no-reset', which controls the
      runtime initialization behavior of the PIC.  More specifically, the presence
      of 'pic-no-reset' mandates that the PIC shall not be reset during runtime
      initialization and that any initialization related to interrupt sources
      shall be limited to sources explicitly referenced in the device tree.  This
      functionality is useful in AMP systems where multiple OSes are sharing the
      PIC and the reinitialization of the PIC can interfere with OSes that are
      already up and running.
      
      The interrupt specifier definition is based off of Stuart Yoder's FSL MPIC
      binding.
      Signed-off-by: NMeador Inge <meador_inge@mentor.com>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: Stuart Yoder <stuart.yoder@freescale.com>
      Cc: Hollis Blanchard <hollis_blanchard@mentor.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a99eff39
  5. 16 3月, 2011 3 次提交
  6. 02 3月, 2011 2 次提交
  7. 28 2月, 2011 1 次提交
  8. 24 2月, 2011 2 次提交
    • S
      rtc: cmos: Add OF bindings · 3bcbaf6e
      Sebastian Andrzej Siewior 提交于
      This allows to load the OF driver based informations from the device
      tree. Systems without BIOS may need to perform some initialization.
      PowerPC creates a PNP device from the OF information and performs this
      kind of initialization in their private PCI quirk. This looks more
      generic.
      
      This patch also avoids registering the platform RTC driver on X86 if
      we have a device tree blob. Otherwise we would setup the device based
      on the hardcoded information in arch/x86 rather than the device tree
      based one.
      
      [ tglx: Changed "int of_have_populated_dt()" to bool as recommended by
              Grant ]
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>
      Acked-by: NGrant Likely <grant.likely@secretlab.ca>
      Cc: sodaville@linutronix.de
      Cc: devicetree-discuss@lists.ozlabs.org
      Cc: rtc-linux@googlegroups.com
      Cc: Alessandro Zummo <a.zummo@towertech.it>
      LKML-Reference: <1298405266-1624-12-git-send-email-bigeasy@linutronix.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      3bcbaf6e
    • S
      x86: dtb: Add a device tree for CE4100 · df2634f4
      Sebastian Andrzej Siewior 提交于
      History:
      v1..v2:
      - dropped device_type except for cpu & pci. I have the compatible string
        for pci so I can drop the device_type once it is possible
      - I lowercased all compatible types. I will need to resend some patches
        which have upper case intel
      - The cpu had the same compatible string as the soc node. So I added to
        the soc node -immr for internel memory mapped registers.
      - I added generic names for all parts.
      - I reworked the i2c bars matching the way you suggested. I added a
        compatible node for the PCI device which only the PCI ids in its
        compatible string. The bars (each represents a complete i2c
        controller) have a "intel,ce4100-i2c-controller" compatible node. It
        is not used by the driver.
        The driver is probed via PCI ids (by the pci subsystem not OF) and
        matches the bar address against the ressource in the child node. Once
        there is a hit the node is attached.
      - The SPI driver is also probed via pci. However I also attached a
        compatible property based on PCI ids
      
      v2..v3:
      - intel,ce4100-immr become intel,ce4100-cp. cp stands for core
        peripherals. The Atom data sheet talks here about ACPI devices. Since
        we don't have ACPI this does not apply here.
      - The interrupt map is gone. There are now plenty of device nodes.
      - The "unit address string" got fixed, it uses not DD,V format.
      
      v3..v4:
      - added descriptions for compatible nodes introduced here:
        - intel,ce4100-ioapic
        - intel,ce4100-lapic
        - intel,ce4100-hpet
        - intel,ce4100
        - intel,ce4100-cp
        - intel,ce4100-pci
      - added a description about I2C controller magic.
      - Added gpio-controller and gpio-cells property to gpio devices. Those
        properties are not (yet) used.
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>
      Acked-by: NGrant Likely <grant.likely@secretlab.ca>
      Cc: sodaville@linutronix.de
      Cc: devicetree-discuss@lists.ozlabs.org
      LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      df2634f4
  9. 23 2月, 2011 2 次提交
  10. 16 2月, 2011 1 次提交
  11. 31 1月, 2011 1 次提交