As we are adding support for the Armada 7K and 8K families, this
commit adds them to the Marvell documentation listing all supported
SoCs, together with references to their Product Brief, Homepage and
Device Tree files.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The Armada 38x Functional Spec is now available (after registration
unfortunately), so add a link to it.

While at it, fix a typo in the reference to the Armada 38x product
page.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

In preparation to the introduction of other SoCs in the ARMv8 Armada
EBU family, this commit tweaks the existing description of Armada 37xx
by making the core, homepage and other informations be visible "under"
the Armada 37xx item. Indeed, the new SoCs will not share the same
core or homepage.

In addition, a link to the Product Brief is added.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

I'm still getting confused regarding which core specifically
is used in which SoC, so I've added some more detail to the
Marvell README file. I got most of this from random sources
on the internet, so it's possible that some of the information
is wrong, but most of it should be pretty obvious.

There are a few remaining points I could not find out:

* The CPU core in Orion 88F6183
* The difference (if any) between PJ4B-MP and PJ4C
* The naming of Feroceon/Jolteon/Flareon/Sheeva/Mohawk/PJ1/PJ4
  is still confusing, as they tend to overlap.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
[Thomas:
 - move Armada SP out from the EBU family into its own "Storage"
   family. This chip is indeed not part of the EBU family.
 - fixed the URL for the Armada SP information, since the link of the
   original patch no longer existed
 - explicitly indicate that there is no support in upstream for the
   Armada SP
 - indent the "Core: " description for the Armada XP to be clearly
   under the Armada XP category, so that it is clear it applies to
   Armada XP only, and not other cores of the EBU family.]
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This patch fix a spelling typo found in clksrc-change-registers.awk.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Now that we support Armada 37xx, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details about
those processors. As for Armda 39x, no datasheet is publicly
available at this time.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.
Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NChen-Yu Tsai <wens@csie.org>
[maxime: Removed the clock protection code]
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The BG2 and BG2Q are no longer listed on Marvell's site, so the links in
the README go nowhere. The BG2Q's product brief has also been removed.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Lots of header files are never included outside of a mach-pxa
directory and do not need to be made visible in include/mach,
so let's just move them all down one level.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Currently kernel crash randomly when K2L EVM is booted without
clk_ignore_unused in the bootargs. This workaround is not needed
on other K2 devices such as K2HK and K2E and with this fix, we can
remove the workaround altogether. netcp driver on K2L uses linked
ram on OSR (On chip Static RAM) and requires the clock to this peripheral
enabled for proper functioning. This is the reason for the kernel crash.
So add the clock node to fix this issue.

While at it, remove the workaround documentation as well.

With the fix applied, clk_summary dump shows the clock to OSR enabled.

cat /sys/kernel/debug/clk/clk_summary
 ------cut--------------
   tcp3d-1                   0            0   399360000          0 0
   tcp3d-0                   0            0   399360000          0 0
   osr                       1            1   399360000          0 0
   fftc-0                    0            0   399360000          0 0
 -----cut----------------
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

The chip's design name isn't hyphenated anywhere else, and none of the
other names in the same document are hyphenated.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Add known information about the Marvell BG2CDP SoC that's used in
the Google Chromecast 2015 and Kinoma HD devices.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Marvell has renamed their Berlin family from "Digital Entertainment" to
"Multimedia Solutions." There aren't proper redirects set up for
device-specific pages, so update the URLs accordingly.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Update the documentation about:
1. Usage of PMU_SPARE2 register.
   Bootloaders on Exynos542x-based boards often use the register
   PMU_SPARE2 (0x908) in the same way as on Exynos3250: as a indicator
   the secondary CPU was booted on. The bootloader will set this value
   to non-zero, after sucessfull power up of secondary CPU. In the same
   time this booted CPU will stuck (spin) waiting for software reset.
2. Exynos542x entry address for secondary CPU boot up after system
   suspend (with MCPM enabled and in non-secure mode).

See arch/arm/mach-exynos/mcpm-exynos.c for source code.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.

In order to have a consistent naming, instead of mentioning the Allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

acc channels are available only if accumulator PDSP is loaded and
running in the SoC. As this requires firmware and user may not have
firmware in the file system, make the accumulator queue support
available in qmss driver optional. To use accumulator queus user needs
to add firmware to the file system and boot up kernel.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

Currently firmware file name is included in the DTS. This is not scalable
as user has to change the DTS if they need upgrade to a new firmware.
Instead, add the firmware file name in the driver itself. As long as there
is no API change, new firmware upgrade is easy and require no driver
change. User is expected to copy the firmware image to the file system
and add a sym link to the new firmware for doing an upgrade. Driver add
a array of firmware file names to search for the available firmware blobs.
This scheme also prepare the driver for future changes to API if ever
happens. In such case it is assumed that driver needs to change to
accommodate the new firmware and new firmware file name will get added to
the array.

Also update the DT document to remove the firmware attribute and add
description about firmware in the driver documentation.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

Add documentation for knav qmss driver.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

Earlier the PBIAS regulator was optional, not so with recent
omap_hsmmc changes. To make things easier for people with
custom .config files, let's add minimal documentation for it
as suggested by Russell King <rmk+kernel@arm.linux.org.uk>.
Signed-off-by: NTony Lindgren <tony@atomide.com>

With the stub to kernel interface being promoted to a proper interface
so that other agents than the stub can boot the kernel proper in EFI
mode, we can remove the linux,uefi-stub-kern-ver field, considering
that its original purpose was to prevent this from happening in the
first place.
Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: NMatt Fleming <matt.fleming@intel.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

Now that we have an efi=debug command line option in the core code, use
this instead of the arm64-specific uefi_debug option.
Signed-off-by: NLeif Lindholm <leif.lindholm@linaro.org>
Acked-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Mark Salter <msalter@redhat.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: NMatt Fleming <matt.fleming@intel.com>

The Victor target has been removed from mainline long ago.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There is a 12MB unused region in our memory map between the vmalloc and
fixmap areas. This became unused with commit e9da6e99, confirmed
with commit 64d3b6a3.

We also have a 8MB guard area before the vmalloc area.  With the default
240MB vmalloc area size and the current VMALLOC_END definition, that
means the end of low memory ends up at 0xef800000 which is unfortunate
for 768MB machines where 8MB of RAM is lost to himem.

Let's move VMALLOC_END to 0xff800000 so the guard area won't chop the
top of the 768MB low memory area while keeping the default vmalloc area
size unchanged and still preserving a gap between the vmalloc and fixmap
areas.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Currently there is no general documentation on Keystone SoCs in the
Linux Documentation folder of the source tree. This patch adds some
essential documentation with links to help users of Keystone Linux and
also provide links to existing documents where necessary.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Add Kconfig entries, header file changes and addition to the documentation.
The early debug infrastructure is also added for easy development.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Switch to my kernel.org alias instead of a badly named gmail address,
which I rarely use.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Extend the kernel-bootloader interface documentation with usage of
register INFORM1 (0x0804) and different CPU resume address on Exynos542x
family (with Multi-Cluster Power Management enabled).

Additionally add glossary and reformat section titles.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

There are some new Allwinner SoCs available, namely A33, A83T and H3.
Update the documentation to mention those and the related documents.
Signed-off-by: NJens Kuske <jenskuske@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Recently wikipedia announced to secure access to the servers.
Now all http access re-route to https.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Various boot loaders for Exynos based boards use certain memory
addresses during booting for different purposes. Mostly this is one of
following :
1. as a CPU boot address,
2. for storing magic cookie related to low power mode (AFTR, sleep).

The document, based solely on kernel source code, tries to group the
information scattered over different files. This would help in the
future when adding support for new SoC or when extending features
related to low power modes.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Since 688d4dfc "perf tools: Support
parsing parameterized events" the perf userspace tools understands
"argument=?" syntax in the events file, making sure that required
arguments are provided by the user and not defaulting to 0, causing
confusion.

This patch adds the required arguments lists for CCN events.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>

This patch adds a "cpumask" attribute to CCN's event_source class sysfs
directory. Perf user tool uses it to restrict events to the
processor(s) enumerated in this mask.

This patch provides a single CPU mask, making it possible to run "-a"
perf session (previously it would request the same CCN event, for
example cycle counter, on each available core and most likely fail).
Initially the mask is set to the CPU that happened to probe the driver,
but it will be changed when it is hot-un-plugged (active events are
migrated to another CPU then).

Example:

 Performance counter stats for 'system wide':

CPU0               2968148      cycles
CPU1               2236736      cycles
CPU2               1797968      cycles
CPU3               1831715      cycles
CPU1            1201850868      ccn/cycles/

       1.001241383 seconds time elapsed
Signed-off-by: NPawel Moll <pawel.moll@arm.com>

The maintainers for mach-msm no longer have any plans to support
or test the platforms supported by this architecture[1]. Most likely
there aren't any active users of this code anyway, so let's
delete it.

[1] http://lkml.kernel.org/r/20150307031212.GA8434@fifo99.com
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Now that we support Armada 39x, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details
about those processors. Unfortunately, no datasheet is publicly
available at this time.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The documentation specified that a machine type is mandatory and made
that assumption in a few places.  However, for DT-only platforms, the
current advice is that no machine type should be registered, so update
accordingly.
Signed-off-by: NGregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Remove ZBOOT MMC/SDHI Documentation for sh7372 together
wit the vrl4 utility. Without sh7372 and Mackerel support
these files are no longer useful.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Everything uses dmaengine now, so there is no reason to
keep this around any longer. Thanks to everyone who was involved
in moving the users over to use the dmaengine APIs.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This patch adds support to STiH418 SoC.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Add a README file to describe Atmel SoCs (aka AT91) support in Mainline Linux:
- SoC list + datasheet web links
- Basic but useful information
- Device Tree conventions and Work In Progress statement.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NOlof Johansson <olof@lixom.net>