- 22 1月, 2011 2 次提交
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由 David Brown 提交于
Allow the timer register to be determined dynamically instead of at compile time. Use common virtual addresses for the registers across all MSM chips, and select the register mappings based on the detected CPU. Signed-off-by: NDavid Brown <davidb@codeaurora.org>
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由 David Brown 提交于
Create runtime queries to distinguish the various MSM targets. Although these would probably be better named soc_is..., use cpu_is... to match convention in the rest of the kernel. Hard code the tests based on config options for now. When runtime device detection is implemented, these can be made dynamic. Signed-off-by: NDavid Brown <davidb@codeaurora.org>
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- 08 1月, 2011 1 次提交
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由 Jeff Ohlstein 提交于
The msm provides timer hardware that is private to each core. Each timer has separate counter and match registers, so we create separate clock_event_devices for each core. For the global clocksource, use cpu 0's counter. Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org>
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- 17 12月, 2010 1 次提交
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由 Pavankumar Kondeti 提交于
Add USB OTG, peripheral and host devices. This patch also adds usb_phy_clk which is required for resetting the PHY. VBUS power up and shutdown routines depends on PMIC module. As PMIC driver is unavailable, configure USB in peripheral only mode. Signed-off-by: NPavankumar Kondeti <pkondeti@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org>
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- 10 12月, 2010 1 次提交
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由 Uwe Kleine-König 提交于
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 03 12月, 2010 1 次提交
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由 Russell King 提交于
This allows us to use smp_cross_call() to trigger a number of different software generated interrupts, rather than combining them all on one SGI. Recover the SGI number via do_IPI. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 01 12月, 2010 3 次提交
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由 Stepan Moskovchenko 提交于
Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Stepan Moskovchenko 提交于
Add register addresses and IRQ numbers for the IOMMU used for the second 2D graphics core. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Stepan Moskovchenko 提交于
On msm8x60, the MID field on the AXI connection to the IOMMU can be up to five bits wide. Thus, allow the IOMMU context platform data to map up to 32 MIDs. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 22 11月, 2010 1 次提交
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由 Anand Gadiyar 提交于
Commit 7c63984b (ARM: do not define VMALLOC_END relative to PAGE_OFFSET) changed VMALLOC_END to be an explicit value. Before this, it was relative to PAGE_OFFSET and therefore converted to unsigned long as PAGE_OFFSET is an unsigned long. This introduced the following build warning. Fix this by changing the explicit defines of VMALLOC_END to be unsigned long. CC arch/arm/mm/init.o arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' Signed-off-by: NAnand Gadiyar <gadiyar@ti.com> Acked-by: NUwe Kleine-K <u.kleine-koenig@pengutronix.dee> Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 11月, 2010 1 次提交
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由 David Brown 提交于
Define VMALLOC_END as an unsigned long to match expected type. Eliminates a warning: arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 30 10月, 2010 2 次提交
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由 Daniel Walker 提交于
If the board has a debug uart the user is given a choice of which uart to use. The user can also select NONE, which means not to use one. In most of our header files when NONE is selected nothing is defined for MSM_DEBUG_UART_PHYS or MSM_DEBUG_UART_BASE. This causes a compile failure in debug-macro.S which expect something to be defined there. Example of the failure, arch/arm/kernel/built-in.o: In function `hexbuf': linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_PHYS' linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_BASE' This fixes the compile failure by adding an ifdef to debug-macro.S that removes all the debug uart code in the case of NONE. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Daniel Walker 提交于
Originally there was an ifdef case to handle when no debug uart was selected. In commit 0ea12930 that case was removed which causes the following build failure, linux-2.6/arch/arm/kernel/debug.S: Assembler messages: linux-2.6/arch/arm/kernel/debug.S:174: Error: bad instruction `addruart r1,r2' linux-2.6/arch/arm/kernel/debug.S:176: Error: bad instruction `waituart r2,r3' linux-2.6/arch/arm/kernel/debug.S:177: Error: bad instruction `senduart r1,r3' linux-2.6/arch/arm/kernel/debug.S:178: Error: bad instruction `busyuart r2,r3' linux-2.6/arch/arm/kernel/debug.S:190: Error: bad instruction `addruart r1,r2' This is a partial revert to add back the case which was removed with two caveats. First the API for the addruart macro was updated, and the new addruart case now return 0xfff00000 so that a know IO mapping is created instead of a random one. Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jason Wang <jason77.wang@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 20 10月, 2010 1 次提交
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由 Jeremy Kerr 提交于
Rather than checking the MMU status in every instance of addruart, do it once in kernel/debug.S, and change the existing addruart macros to return both physical and virtual addresses. The main debug code can then select the appropriate address to use. This will also allow us to retreive the address of a uart for the MMU state that we're not current in. Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com> and Tony Lindgren <tony@atomide.com>, and fix for versatile express from Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>. Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NJason Wang <jason77.wang@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com> Tested-by: NKevin Hilman <khilman@deeprootsystems.com>
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- 09 10月, 2010 11 次提交
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由 Stepan Moskovchenko 提交于
Add the platform data for the IOMMUs found on the Qualcomm msm8x60 SoC. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Stepan Moskovchenko 提交于
Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Jeff Ohlstein 提交于
The MSM8x60 has a different physical memory offset than other targets. Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Daniel Walker 提交于
Some MSM targets don't select the debug UART in this way. For those we need to disable this selection mechanism. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
The existing MSM irq entry macro is specific to a VIC implementation. Renaming this makes room for irq support based on other interrupt controllers. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
Board configuration for MSM8X60 emulation on RUMI3. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Jeff Ohlstein 提交于
Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Abhijeet Dharmapurikar 提交于
Define the interrupt map in irq-8x60.h Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
IRQ assignments are different for MSM8X60 than other existing MSMs. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
MSM8X60 has different IO mappings than previous MSMs. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 07 10月, 2010 2 次提交
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由 Gregory Bean 提交于
Now that all supported gpio_tlmm_config-using boards are using gpiomux, remove the deprecated code. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Gregory Bean 提交于
Add the 'gpiomux' api, which addresses the following shortcomings of existing tlmm api: - gpio power-collapse, which is managed by a peripheral processor on other targets, must be managed by the application processor on the 8x60. - The enable/disable flag of the legacy gpio_tlmm_config api is not applicable on the 8x60, and causes confusion. - The gpio 'direction' bits are meaningless for all func_sel configurations except for generic-gpio mode (func_sel 0), in which case the gpio_direction_* functions should be used. Having these bits in the tlmm api leads to confusion and misuse of the gpiolib api, and they have been removed in gpiomux. - The functional api of the legacy system ran contrary to the typical use-case, which is a single massive configuration at boot. Rather than forcing hundreds of 'config' function calls, the new api allows data to be configured with a single table. gpiomux_get and gpiomux_put are meant to be called automatically when gpio_request and gpio_free are called, giving automatic gpiomux/tlmm control to those drivers/lines with simple power profiles - in the simplest cases, an entry in the gpiomux table and the correct usage of gpiolib is all that is required to get proper gpio power control. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 02 10月, 2010 1 次提交
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由 Nicolas Pitre 提交于
VMALLOC_END is supposed to be an absolute value, while PAGE_OFFSET may vary depending on the selected user:kernel memory split mode through CONFIG_VMSPLIT_*. In fact, the goal of moving PAGE_OFFSET down is to accommodate more directly addressed RAM by the kernel below the vmalloc area, and having VMALLOC_END move along PAGE_OFFSET is rather against the very reason why PAGE_OFFSET can be moved in the first place. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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- 10 8月, 2010 2 次提交
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由 Sahitya Tummala 提交于
Rename mmc_platform_data to msm_mmc_platform_data as it is used only by MSM platform. Signed-off-by: NSahitya Tummala <stummala@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Sahitya Tummala 提交于
Add msm_add_sdcc() prototype to mach/board.h to fix the checkpatch warning. Signed-off-by: NSahitya Tummala <stummala@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 16 6月, 2010 1 次提交
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由 Pavel Machek 提交于
Signed-off-by: NPavel Machek <pavel@ucw.cz> [dwalker@codeaurora.org: renamed to trout, checkpatch cleanup] Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 14 5月, 2010 9 次提交
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由 Daniel Walker 提交于
The MSM7x30 does not have a separate bank of memory for shared memory communication with the radio CPU. Set the kernel base address 2MB in, to use this first 2MB for this purpose. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
The MSM SOC's DMA controller contains several security domains. On the MSM7x00, only security domain 3 is accessible to our CPU. The 7x30, however, uses security domain 2. Fix up the register definition macros to select this appropriately, based on configured target. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Add a header describing the io regions for MSM7x30. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Support different RAM base addresses used by Qualcomm SOCs, with QSD8x50 as the first addtional one. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Add a header describing the io regions for QSD8x50. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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