- 03 4月, 2013 2 次提交
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由 Guennadi Liakhovetski 提交于
Add a DT node for the SMSC 9221 ethernet chip, found on kzm9g, to its reference implementation. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
Add basic Bock-W board support More devices will be added on top of this patch after PICNTRL and clock framework are in better shape. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 02 4月, 2013 9 次提交
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由 Takashi Yoshii 提交于
The r8a7790 SoC supports LPAE and has memory window up to 0x2ffffffff. Convert to 64-bit addresses by enlarging #addr-cells and #size-cells to 2. Signed-off-by: NTakashi Yoshii <takashi.yoshii.zj@renesas.com> Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Takashi Yoshii 提交于
The r8a73a4 SoC supports LPAE and has memory window up to 0x2ffffffff. Convert to 64-bit addresses by enlarging #addr-cells and #size-cells to 2. Signed-off-by: NTakashi Yoshii <takashi.yoshii.zj@renesas.com> Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Add IRQC interrupt controller support to r8a7790 by hooking up a single IRQC instances to handle 4 external IRQ signals. The IRQC controller is tied to SPIs of the GIC. On r8a7790 the external IRQ pins routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Add initial support for the r8a7790 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
You can get current thermal by > cat /sys/class/thermal/thermal_zone?/temp Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Guennadi Liakhovetski 提交于
Add DT nodes for the 4 irqpin interrupt controllers on sh73a0. We add them to sh73a0.dtsi, which is also used by configurations, doing all their device instantiation from board the .c code. We rely on the fact, that such configurations don't instantiate devices from the device-tree. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
Add initial support for the R8A7778 R-Car M1A SoC. No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. It is based on v1.0 datasheet Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
V3 of initial support for the r8a73a4 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 21 3月, 2013 3 次提交
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由 Guennadi Liakhovetski 提交于
Fix several device-tree bindings, that haven't been updated for newest versions of respective drivers, and device names and pin numbers, left over from non-DT and old pinctrl versions. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Guennadi Liakhovetski 提交于
To avoid having to repeat common DT node properties in all .dts files move them to SoC's .dtsi file, setting their status to "disabled." Individual boards will pick up devices, that they want to use and change their DT node status to enabled. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Guennadi Liakhovetski 提交于
kzm9g supplies 3.3V to its SDHI0 and SDHI2 interfaces. Specifying 2.8V prevents some (e.g. certain SDIO) cards from working. This patch fixes the voltage and removes redundant OCR masks from platform data. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 18 3月, 2013 3 次提交
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由 Guennadi Liakhovetski 提交于
Add SDHI0 and SDHI2 interfaces to kzm9g-reference. With no pinctrl DT support we cannot use GPIO card-detection and regulator switching. Also update the MMCIF DT node to use all 8 data lines and avoid redundant information in DT. Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> [ horms+renesas@verge.net.au: Updated for pinmux changes by Laurent Pinchart ] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
Provide alternate board code for the kzm9g to demonstrate how DT may be used given the current state of driver device tree support. This is intended to act as a reference for mach-shmobile developers. Some notes: * Brings up the GIC interrupt handler using device tree * Brings up the following device using device tree: - MMCIF (MMC) * Does not bring up the INTC interrupt controller at all, thus external devices may not be used. In particular, the SMSC ethernet device may not be used and thus NFS root may not be used. * Uses existing C code and not device tree to initialise the following, which are needed for a working board: - SCIF (Serial) - CMT (Clock) - PFC (GPIO) To use this alternate board code instead of the normal board code, CONFIG_MACH_KZM9G_REFERENCE should be selected in the kernel config. And the sh73a0-kzm9g-reference.dtb flattened device tree blob should be used. Includes fix by Thierry Reding to no longer use gic_handle_irq() Includes fixes by Guennadi Liakhovetski for recent pinmux changes. Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
Provide alternate board code for the marzen to demonstrate how DT may be used given the current state of driver device tree support. This is intended to act as a reference for mach-shmobile developers. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 13 3月, 2013 6 次提交
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由 Vladimir Barinov 提交于
Allow configuration of the r8a7779 SoC SATA controller using a flattened device tree. Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
76cc1887 (thermal: rcar: add Device Tree support) supported rcar_thermal DT probing. rcar thermal driver doesn't support IRQ on r8a7779 chip since it is using old design IRQ. R-Car/R-Mobile next generation chips are using new design IRQ, and rcar thermal driver is supporting these. This patch adds rcar_thermal DT support for r8a7779 without IRQ. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
r8a7779 is not r8a7740 chip Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
The ethernet controller is not part of the r8a7779 SoC. Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
Allow a minimal setup of the r8a7779 SoC using a flattened device tree. In particular, configure the i2c and ethernet controllers using a flattened device tree. SCI serial controller and TMU clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. The ethernet controller also requires a regulator which is a board property. A sample snippet DT for the marzen board is as follows: /dts-v1/; /include/ "r8a7779.dtsi" / { fixedregulator3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; &lan0 { vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
This allows the GIC interrupt controller of the r8a7779 SoC to be initialised using a flattened device tree blob. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> --- v3 * Fix copy-paste error and use unique reg values for each CPU v2 As suggested by Mark Rutland * Add reg and device_type to cpus * Remove #address-cells from gic
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- 07 3月, 2013 2 次提交
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由 Haojian Zhuang 提交于
Add gpio offset into "gpio-range-cells" property. It's used to support sparse pinctrl range in gpio chip. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jonathan Austin 提交于
Before jumping to (position independent) C-code from the decompressor's assembler world we set-up the C environment. This setup currently does not set r9, which for arm-none-uclinux-uclibceabi toolchains is by default expected to be the PIC offset base register (IE should point to the beginning of the GOT). Currently, therefore, in order to build working kernels that use the decompressor it is necessary to use an arm-linux-gnueabi toolchain, or similar. uClinux toolchains cause a prefetch abort to occur at the beginning of the decompress_kernel function. This patch allows uClinux toolchains to build bootable zImages by forcing the -mno-single-pic-base option, which ensures that the location of the GOT is re-derived each time it is required, and r9 becomes free for use as a general purpose register. This has a small (4% in instruction terms) advantage over the alternative of setting r9 to point to the GOT before calling into the C-world. Signed-off-by: NJonathan Austin <jonathan.austin@arm.com> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 01 3月, 2013 15 次提交
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由 Florian Fainelli 提交于
The Armada 370 Reference Design board has one SD card slot, directly connected to the SDIO IP of the SoC, so we enable this IP. there are no GPIOs for card-detect and write-protect so we do not specify any. Signed-off-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jason Cooper 提交于
Signed-off-by: NJason Cooper <jason@lakedaemon.net> Tested-by: NAndrew Lunn <andrew@lunn.ch>
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由 Jason Cooper 提交于
Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
Add a DT node for I2C and pinctrl hog for the pins. There appears to be an i2c bus on topkick with a device on it: i2cdetect 0 WARNING! This program can confuse your I2C bus, cause data loss and worse! I will probe file /dev/i2c-0. I will probe address range 0x03-0x77. Continue? [Y/n] y 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jason Cooper 提交于
Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
of_serial now has support for using clocks property and we have a DT clock provider. This patch replaces the hard coded clock-frequency property with a clocks phandle to tclk. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
This patch add support for the SPI flash MX25l25635E which is present on the Armada 370 DB board. This flash stores the bootloader and its environment. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
This patch add support for the SPI flash M25P64 which is present on the Armada XP DB board. This flash stores the bootloader and its environment. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
This patch adds an SPI master device node for Armada XP-GP board. This master node is an SPI flash controller 'n25q128a13'. Since there is no 'partitions' node declared, one full sized partition named as the device will be created. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Lior Amsalem <alior@marvell.com> Tested-by: NGregory Clement <gregory.clement@free-electrons.com> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: NGregory Clement <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
The Armada 370 and Armada XP SoC has an SPI controller. This patch adds support for this controller in Armada 370 and Armada XP SoC common device tree files. Note that the Armada XP SPI register length is 0x50 bytes, while Armada 370 SPI register length is 0x28 bytes, so we choose the smaller of the two. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Lior Amsalem <alior@marvell.com> Acked-by: NGregory Clement <gregory.clement@free-electrons.com> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
Now that the time-armada-370-xp support local timers, updated the device tree to take it into account. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
With DT support for orion-ehci also convert Dove to it and remove the legacy calls and clock aliases. This patch is based on "ARM: Dove: split legacy and DT setup" applied to mvebu/boards recently. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
This patch activates every USB port provided by each SoC. Except for Armada XP Openblocks AX3-4 board, where we enable only the first two USB ports until we have more information on the third one usage. Cc: Lior Amsalem <alior@marvell.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
The Armada 370 and Armada XP SoC has an Orion EHCI USB controller. This patch adds support for this controller in Armada 370 and Armada XP SoC common device tree files. Cc: Lior Amsalem <alior@marvell.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The OpenBlocks AX3-4 board has one software-controlled button on the front side, labeled "INIT", so we add minimal support for this button in the kernel. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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