1. 02 12月, 2014 2 次提交
  2. 23 10月, 2014 4 次提交
  3. 09 10月, 2014 3 次提交
  4. 30 9月, 2014 1 次提交
    • B
      mpc85xx_edac: Make L2 interrupt shared too · a18c3f16
      Borislav Petkov 提交于
      The other two interrupt handlers in this driver are shared, except this
      one. When loading the driver, it fails like this.
      
      So make the IRQ line shared.
      
      Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software
      mpc85xx_mc_err_probe: No ECC DIMMs discovered
      EDAC DEVICE0: Giving out device to module MPC85xx_edac controller mpc85xx_l2_err: DEV mpc85xx_l2_err (INTERRUPT)
      genirq: Flags mismatch irq 16. 00000000 ([EDAC] L2 err) vs. 00000080 ([EDAC] PCI err)
      mpc85xx_l2_err_probe: Unable to request irq 16 for MPC85xx L2 err
      remove_proc_entry: removing non-empty directory 'irq/16', leaking at least 'aerdrv'
      ------------[ cut here ]------------
      WARNING: at fs/proc/generic.c:521
      Modules linked in:
      CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.17.0-rc5-dirty #1
      task: ee058000 ti: ee046000 task.ti: ee046000
      NIP: c016c0c4 LR: c016c0c4 CTR: c037b51c
      REGS: ee047c10 TRAP: 0700 Not tainted (3.17.0-rc5-dirty)
      MSR: 00029000 <CE,EE,ME> CR: 22008022 XER: 20000000
      
      GPR00: c016c0c4 ee047cc0 ee058000 00000053 00029000 00000000 c037c744 00000003
      GPR08: c09aab28 c09aab24 c09aab28 00000156 20008028 00000000 c0002ac8 00000000
      GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 00000139 c0950394
      GPR24: c09f0000 ee5585b0 ee047d08 c0a10000 ee047d08 ee15f808 00000002 ee03f660
      NIP [c016c0c4] remove_proc_entry
      LR [c016c0c4] remove_proc_entry
      Call Trace:
      remove_proc_entry (unreliable)
      unregister_irq_proc
      free_desc
      irq_free_descs
      mpc85xx_l2_err_probe
      platform_drv_probe
      really_probe
      __driver_attach
      bus_for_each_dev
      bus_add_driver
      driver_register
      mpc85xx_mc_init
      do_one_initcall
      kernel_init_freeable
      kernel_init
      ret_from_kernel_thread
      Instruction dump: ...
      
      Reported-and-tested-by: <lpb_098@163.com>
      Acked-by: NJohannes Thumshirn <johannes.thumshirn@men.de>
      Cc: stable@vger.kernel.org
      Signed-off-by: NBorislav Petkov <bp@suse.de>
      a18c3f16
  5. 23 9月, 2014 1 次提交
    • A
      amd64_edac: Modify usage of amd64_read_dct_pci_cfg() · 7981a28f
      Aravind Gopalakrishnan 提交于
      Rationale behind this change:
       - F2x1xx addresses were stopped from being mapped explicitly to DCT1
         from F15h (OR) onwards. They use _dct[0:1] mechanism to access the
         registers. So we should move away from using address ranges to select
         DCT for these families.
       - On newer processors, the address ranges used to indicate DCT1 (0x140,
         0x1a0) have different meanings than what is assumed currently.
      
      Changes introduced:
       - amd64_read_dct_pci_cfg() now takes in dct value and uses it for
         'selecting the dct'
       - Update usage of the function. Keep in mind that different families
         have specific handling requirements
       - Remove [k8|f10]_read_dct_pci_cfg() as they don't do much different
         from amd64_read_pci_cfg()
         - Move the k8 specific check to amd64_read_pci_cfg
       - Remove f15_read_dct_pci_cfg() and move logic to amd64_read_dct_pci_cfg()
       - Remove now needless .read_dct_pci_cfg
      
      Testing:
       - Tested on Fam 10h; Fam15h Models: 00h, 30h; Fam16h using 'EDAC_DEBUG'
         and mce_amd_inj
       - driver obtains info from F2x registers and caches it in pvt
         structures correctly
       - ECC decoding works fine
      Signed-off-by: NAravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
      Link: http://lkml.kernel.org/r/1410799058-3149-1-git-send-email-aravind.gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
      7981a28f
  6. 15 9月, 2014 1 次提交
  7. 05 9月, 2014 1 次提交
  8. 02 9月, 2014 1 次提交
  9. 14 7月, 2014 1 次提交
  10. 10 7月, 2014 1 次提交
  11. 04 7月, 2014 2 次提交
  12. 27 6月, 2014 12 次提交
  13. 24 6月, 2014 2 次提交
  14. 31 5月, 2014 1 次提交
  15. 30 5月, 2014 1 次提交
  16. 09 5月, 2014 2 次提交
  17. 01 4月, 2014 2 次提交
  18. 13 3月, 2014 2 次提交