1. 13 7月, 2015 17 次提交
    • H
      s390/nmi: fix vector register corruption · cad49cfc
      Heiko Carstens 提交于
      If a machine check happens, the machine has the vector facility installed
      and the extended save area exists, the cpu will save vector register
      contents into the extended save area. This is regardless of control
      register 0 contents, which enables and disables the vector facility during
      runtime.
      
      On each machine check we should validate the vector registers. The current
      code however tries to validate the registers only if the running task is
      using vector registers in user space.
      
      However even the current code is broken and causes vector register
      corruption on machine checks, if user space uses them:
      the prefix area contains a pointer (absolute address) to the machine check
      extended save area. In order to save some space the save area was put into
      an unused area of the second prefix page.
      When validating vector register contents the code uses the absolute address
      of the extended save area, which is wrong. Due to prefixing the vector
      instructions will then access contents using absolute addresses instead
      of real addresses, where the machine stored the contents.
      
      If the above would work there is still the problem that register validition
      would only happen if user space uses vector registers. If kernel space uses
      them also, this may also lead to vector register content corruption:
      if the kernel makes use of vector instructions, but the current running
      user space context does not, the machine check handler will validate
      floating point registers instead of vector registers.
      Given the fact that writing to a floating point register may change the
      upper halve of the corresponding vector register, we also experience vector
      register corruption in this case.
      
      Fix all of these issues, and always validate vector registers on each
      machine check, if the machine has the vector facility installed and the
      extended save area is defined.
      
      Cc: <stable@vger.kernel.org> # 4.1+
      Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      cad49cfc
    • H
      s390/process: fix sfpc inline assembly · e47994dd
      Heiko Carstens 提交于
      The sfpc inline assembly within execve_tail() may incorrectly set bits
      28-31 of the sfpc instruction to a value which is not zero.
      These bits however are currently unused and therefore should be zero
      so we won't get surprised if these bits will be used in the future.
      
      Therefore remove the second operand from the inline assembly.
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      e47994dd
    • V
      ARCv2: support HS38 releases · 624b71ee
      Vineet Gupta 提交于
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      624b71ee
    • A
      ARC: make sure instruction_pointer() returns unsigned value · f51e2f19
      Alexey Brodkin 提交于
      Currently instruction_pointer() returns pt_regs->ret and so return value
      is of type "long", which implicitly stands for "signed long".
      
      While that's perfectly fine when dealing with 32-bit values if return
      value of instruction_pointer() gets assigned to 64-bit variable sign
      extension may happen.
      
      And at least in one real use-case it happens already.
      In perf_prepare_sample() return value of perf_instruction_pointer()
      (which is an alias to instruction_pointer() in case of ARC) is assigned
      to (struct perf_sample_data)->ip (which type is "u64").
      
      And what we see if instuction pointer points to user-space application
      that in case of ARC lays below 0x8000_0000 "ip" gets set properly with
      leading 32 zeros. But if instruction pointer points to kernel address
      space that starts from 0x8000_0000 then "ip" is set with 32 leadig
      "f"-s. I.e. id instruction_pointer() returns 0x8100_0000, "ip" will be
      assigned with 0xffff_ffff__8100_0000. Which is obviously wrong.
      
      In particular that issuse broke output of perf, because perf was unable
      to associate addresses like 0xffff_ffff__8100_0000 with anything from
      /proc/kallsyms.
      
      That's what we used to see:
       ----------->8----------
        6.27%  ls       [unknown]                [k] 0xffffffff8046c5cc
        2.96%  ls       libuClibc-0.9.34-git.so  [.] memcpy
        2.25%  ls       libuClibc-0.9.34-git.so  [.] memset
        1.66%  ls       [unknown]                [k] 0xffffffff80666536
        1.54%  ls       libuClibc-0.9.34-git.so  [.] 0x000224d6
        1.18%  ls       libuClibc-0.9.34-git.so  [.] 0x00022472
       ----------->8----------
      
      With that change perf output looks much better now:
       ----------->8----------
        8.21%  ls       [kernel.kallsyms]        [k] memset
        3.52%  ls       libuClibc-0.9.34-git.so  [.] memcpy
        2.11%  ls       libuClibc-0.9.34-git.so  [.] malloc
        1.88%  ls       libuClibc-0.9.34-git.so  [.] memset
        1.64%  ls       [kernel.kallsyms]        [k] _raw_spin_unlock_irqrestore
        1.41%  ls       [kernel.kallsyms]        [k] __d_lookup_rcu
       ----------->8----------
      Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      Cc: arc-linux-dev@synopsys.com
      Cc: stable@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      f51e2f19
    • G
      m68k: enable PCI support for m5475evb defconfig · 67592f69
      Greg Ungerer 提交于
      The ColdFire M5475 on the m5475evb board supports a PCI bus, lets
      enable it for the defconfig to get better build and test coverage.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      67592f69
    • G
      m68k: fix io functions for ColdFire/MMU/PCI case · 03aa29f8
      Greg Ungerer 提交于
      The inb/outb/... family of IO methods end up being multiply defined when
      building PCI support for the ColdFire. Compiling gives this:
      
        CC      init/main.o
      In file included from ./arch/m68k/include/asm/io.h:4:0,
                       from include/linux/bio.h:30,
                       from include/linux/blkdev.h:18,
                       from init/main.c:75:
      ./arch/m68k/include/asm/io_mm.h:420:0: warning: "inb" redefined
      ./arch/m68k/include/asm/io_mm.h:108:0: note: this is the location of the previous definition
      ...
      
      The ColdFire/PCI case defines its own IO access methods, so no others
      should be defined or used in this case. Conditionally disable other
      definitions that clash with it.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      03aa29f8
    • G
      m68knommu: update defconfig for ColdFire m5475evb · 8700f094
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      8700f094
    • G
      m68knommu: update defconfig for ColdFire m5407c3 · fee53922
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      fee53922
    • G
      m68knommu: update defconfig for ColdFire m5307c3 · 59c024b7
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      59c024b7
    • G
      m68knommu: update defconfig for ColdFire m5275evb · 6845f6e1
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      6845f6e1
    • G
      m68knommu: update defconfig for ColdFire m5272c3 · 2e27f443
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      2e27f443
    • G
      m68knommu: update defconfig for ColdFire m5249evb · 0f28b05a
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      0f28b05a
    • G
      m68knommu: update defconfig for m5208evb · bfd302ac
      Greg Ungerer 提交于
      No change to active configuration settings, updated to match current
      Kconfigs only.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      bfd302ac
    • G
      m68knommu: make ColdFire SoC selection a choice · fa95a1dd
      Greg Ungerer 提交于
      It would be nice if we could support multiple ColdFire SoC types in a
      single binary - but currently the code simply does not support it.
      Change the SoC selection config options to be a choice instead of
      individual selectable entries.
      
      This fixes problems with building allnoconfig, and means that a sane
      linux kernel is generated for a single ColdFire SoC type.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      fa95a1dd
    • G
      m68knommu: improve the clock configuration defaults · 15c2ca4e
      Greg Ungerer 提交于
      Create some intelligent default settings for each ColdFire SoC type
      in the configuration entry for CONFIG_CLOCK_FREQ.
      
      The ColdFire clock frequency is configurable at build time. There is a
      lot of variation in the frequency of operation on specific ColdFire based
      boards. But we can choose a default that matches the maximum frequency
      of clock operation for a particular ColdFire part. That is typically
      the most common clock setting.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      15c2ca4e
    • G
      m68knommu: force setting of CONFIG_CLOCK_FREQ for ColdFire · d9ee4896
      Greg Ungerer 提交于
      It is possible to disable the clock selection at configuration time,
      but for ColdFire targets we always expect a clock frequency to be
      selected. This results in the following compile time error:
      
        CC      arch/m68k/kernel/asm-offsets.s
      In file included from ./arch/m68k/include/asm/timex.h:14:0,
                       from include/linux/timex.h:65,
                       from include/linux/sched.h:19,
                       from arch/m68k/kernel/asm-offsets.c:14:
      ./arch/m68k/include/asm/coldfire.h:25:2: error: #error "Don't know what your ColdFire CPU clock frequency is??"
      
      Remove CONFIG_CLOCK_SELECT completely and always enable CONFIG_CLOCK_FREQ
      for ColdFire.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      d9ee4896
    • R
      ARM: dts: dra7x-evm: Prevent glitch on DCAN1 pinmux · 2acb5c30
      Roger Quadros 提交于
      Driver core sets "default" pinmux on on probe and CAN driver
      sets "sleep" pinmux during register. This causes a small window
      where the CAN pins are in "default" state with the DCAN module
      being disabled.
      
      Change the "default" state to be like sleep so this glitch is
      avoided. Add a new "active" state that is used by the driver
      when CAN is actually active.
      Signed-off-by: NRoger Quadros <rogerq@ti.com>
      Cc: linux-stable <stable@vger.kernel.org>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      2acb5c30
  2. 11 7月, 2015 1 次提交
    • J
      parisc: Fix some PTE/TLB race conditions and optimize __flush_tlb_range based on timing results · 01ab6057
      John David Anglin 提交于
      The increased use of pdtlb/pitlb instructions seemed to increase the
      frequency of random segmentation faults building packages. Further, we
      had a number of cases where TLB inserts would repeatedly fail and all
      forward progress would stop. The Haskell ghc package caused a lot of
      trouble in this area. The final indication of a race in pte handling was
      this syslog entry on sibaris (C8000):
      
       swap_free: Unused swap offset entry 00000004
       BUG: Bad page map in process mysqld  pte:00000100 pmd:019bbec5
       addr:00000000ec464000 vm_flags:00100073 anon_vma:0000000221023828 mapping: (null) index:ec464
       CPU: 1 PID: 9176 Comm: mysqld Not tainted 4.0.0-2-parisc64-smp #1 Debian 4.0.5-1
       Backtrace:
        [<0000000040173eb0>] show_stack+0x20/0x38
        [<0000000040444424>] dump_stack+0x9c/0x110
        [<00000000402a0d38>] print_bad_pte+0x1a8/0x278
        [<00000000402a28b8>] unmap_single_vma+0x3d8/0x770
        [<00000000402a4090>] zap_page_range+0xf0/0x198
        [<00000000402ba2a4>] SyS_madvise+0x404/0x8c0
      
      Note that the pte value is 0 except for the accessed bit 0x100. This bit
      shouldn't be set without the present bit.
      
      It should be noted that the madvise system call is probably a trigger for many
      of the random segmentation faults.
      
      In looking at the kernel code, I found the following problems:
      
      1) The pte_clear define didn't take TLB lock when clearing a pte.
      2) We didn't test pte present bit inside lock in exception support.
      3) The pte and tlb locks needed to merged in order to ensure consistency
      between page table and TLB. This also has the effect of serializing TLB
      broadcasts on SMP systems.
      
      The attached change implements the above and a few other tweaks to try
      to improve performance. Based on the timing code, TLB purges are very
      slow (e.g., ~ 209 cycles per page on rp3440). Thus, I think it
      beneficial to test the split_tlb variable to avoid duplicate purges.
      Probably, all PA 2.0 machines have combined TLBs.
      
      I dropped using __flush_tlb_range in flush_tlb_mm as I realized all
      applications and most threads have a stack size that is too large to
      make this useful. I added some comments to this effect.
      
      Since implementing 1 through 3, I haven't had any random segmentation
      faults on mx3210 (rp3440) in about one week of building code and running
      as a Debian buildd.
      Signed-off-by: NJohn David Anglin <dave.anglin@bell.net>
      Cc: stable@vger.kernel.org # v3.18+
      Signed-off-by: NHelge Deller <deller@gmx.de>
      01ab6057
  3. 10 7月, 2015 15 次提交
    • M
      arm64: entry32: remove pointless register assignment · ad2daa85
      Mark Rutland 提交于
      We currently set x27 in compat_sys_sigreturn_wrapper and
      compat_sys_rt_sigreturn_wrapper, similarly to what we do with r8/why on
      32-bit ARM, in an attempt to prevent sigreturns from being restarted.
      
      However, on arm64 we have always used pt_regs::syscallno for syscall
      restarting (for both native and compat tasks), and x27 is never
      inspected again before being overwritten in kernel_exit.
      
      This patch removes the pointless register assignments.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      ad2daa85
    • W
      kvm: x86: fix load xsave feature warning · ee4100da
      Wanpeng Li 提交于
      [   68.196974] WARNING: CPU: 1 PID: 2140 at arch/x86/kvm/x86.c:3161 kvm_arch_vcpu_ioctl+0xe88/0x1340 [kvm]()
      [   68.196975] Modules linked in: snd_hda_codec_hdmi i915 rfcomm bnep bluetooth i2c_algo_bit rfkill nfsd drm_kms_helper nfs_acl nfs drm lockd grace sunrpc fscache snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_seq_dummy snd_seq_oss x86_pkg_temp_thermal snd_seq_midi kvm_intel snd_seq_midi_event snd_rawmidi kvm snd_seq ghash_clmulni_intel fuse snd_timer aesni_intel parport_pc ablk_helper snd_seq_device cryptd ppdev snd lp parport lrw dcdbas gf128mul i2c_core glue_helper lpc_ich video shpchp mfd_core soundcore serio_raw acpi_cpufreq ext4 mbcache jbd2 sd_mod crc32c_intel ahci libahci libata e1000e ptp pps_core
      [   68.197005] CPU: 1 PID: 2140 Comm: qemu-system-x86 Not tainted 4.2.0-rc1+ #2
      [   68.197006] Hardware name: Dell Inc. OptiPlex 7020/0F5C5X, BIOS A03 01/08/2015
      [   68.197007]  ffffffffa03b0657 ffff8800d984bca8 ffffffff815915a2 0000000000000000
      [   68.197009]  0000000000000000 ffff8800d984bce8 ffffffff81057c0a 00007ff6d0001000
      [   68.197010]  0000000000000002 ffff880211c1a000 0000000000000004 ffff8800ce0288c0
      [   68.197012] Call Trace:
      [   68.197017]  [<ffffffff815915a2>] dump_stack+0x45/0x57
      [   68.197020]  [<ffffffff81057c0a>] warn_slowpath_common+0x8a/0xc0
      [   68.197022]  [<ffffffff81057cfa>] warn_slowpath_null+0x1a/0x20
      [   68.197029]  [<ffffffffa037bed8>] kvm_arch_vcpu_ioctl+0xe88/0x1340 [kvm]
      [   68.197035]  [<ffffffffa037aede>] ? kvm_arch_vcpu_load+0x4e/0x1c0 [kvm]
      [   68.197040]  [<ffffffffa03696a6>] kvm_vcpu_ioctl+0xc6/0x5c0 [kvm]
      [   68.197043]  [<ffffffff811252d2>] ? perf_pmu_enable+0x22/0x30
      [   68.197044]  [<ffffffff8112663e>] ? perf_event_context_sched_in+0x7e/0xb0
      [   68.197048]  [<ffffffff811a6882>] do_vfs_ioctl+0x2c2/0x4a0
      [   68.197050]  [<ffffffff8107bf33>] ? finish_task_switch+0x173/0x220
      [   68.197053]  [<ffffffff8123307f>] ? selinux_file_ioctl+0x4f/0xd0
      [   68.197055]  [<ffffffff8122cac3>] ? security_file_ioctl+0x43/0x60
      [   68.197057]  [<ffffffff811a6ad9>] SyS_ioctl+0x79/0x90
      [   68.197060]  [<ffffffff81597e57>] entry_SYSCALL_64_fastpath+0x12/0x6a
      [   68.197061] ---[ end trace 558a5ebf9445fc80 ]---
      
      After commit (0c4109be 'x86/fpu/xstate: Fix up bad get_xsave_addr()
      assumptions'), there is no assumption an xsave bit is present in the
      hardware (pcntxt_mask) that it is always present in a given xsave buffer.
      An enabled state to be present on 'pcntxt_mask', but *not* in 'xstate_bv'
      could happen when the last 'xsave' did not request that this feature be
      saved (unlikely) or because the "init optimization" caused it to not be
      saved. This patch kill the assumption.
      Signed-off-by: NWanpeng Li <wanpeng.li@hotmail.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      ee4100da
    • P
      KVM: x86: apply guest MTRR virtualization on host reserved pages · fd717f11
      Paolo Bonzini 提交于
      Currently guest MTRR is avoided if kvm_is_reserved_pfn returns true.
      However, the guest could prefer a different page type than UC for
      such pages. A good example is that pass-throughed VGA frame buffer is
      not always UC as host expected.
      
      This patch enables full use of virtual guest MTRRs.
      Suggested-by: NXiao Guangrong <guangrong.xiao@linux.intel.com>
      Tested-by: Joerg Roedel <jroedel@suse.de> (on AMD)
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      fd717f11
    • J
      KVM: SVM: Sync g_pat with guest-written PAT value · e098223b
      Jan Kiszka 提交于
      When hardware supports the g_pat VMCB field, we can use it for emulating
      the PAT configuration that the guest configures by writing to the
      corresponding MSR.
      Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
      Tested-by: NJoerg Roedel <jroedel@suse.de>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      e098223b
    • P
      KVM: SVM: use NPT page attributes · 3c2e7f7d
      Paolo Bonzini 提交于
      Right now, NPT page attributes are not used, and the final page
      attribute depends solely on gPAT (which however is not synced
      correctly), the guest MTRRs and the guest page attributes.
      
      However, we can do better by mimicking what is done for VMX.
      In the absence of PCI passthrough, the guest PAT can be ignored
      and the page attributes can be just WB.  If passthrough is being
      used, instead, keep respecting the guest PAT, and emulate the guest
      MTRRs through the PAT field of the nested page tables.
      
      The only snag is that WP memory cannot be emulated correctly,
      because Linux's default PAT setting only includes the other types.
      Tested-by: NJoerg Roedel <jroedel@suse.de>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      3c2e7f7d
    • P
      KVM: count number of assigned devices · 5544eb9b
      Paolo Bonzini 提交于
      If there are no assigned devices, the guest PAT are not providing
      any useful information and can be overridden to writeback; VMX
      always does this because it has the "IPAT" bit in its extended
      page table entries, but SVM does not have anything similar.
      Hook into VFIO and legacy device assignment so that they
      provide this information to KVM.
      Reviewed-by: NAlex Williamson <alex.williamson@redhat.com>
      Tested-by: NJoerg Roedel <jroedel@suse.de>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      5544eb9b
    • R
      KVM: VMX: fix vmwrite to invalid VMCS · 370777da
      Radim Krčmář 提交于
      fpu_activate is called outside of vcpu_load(), which means it should not
      touch VMCS, but fpu_activate needs to.  Avoid the call by moving it to a
      point where we know that the guest needs eager FPU and VMCS is loaded.
      
      This will get rid of the following trace
      
       vmwrite error: reg 6800 value 0 (err 1)
        [<ffffffff8162035b>] dump_stack+0x19/0x1b
        [<ffffffffa046c701>] vmwrite_error+0x2c/0x2e [kvm_intel]
        [<ffffffffa045f26f>] vmcs_writel+0x1f/0x30 [kvm_intel]
        [<ffffffffa04617e5>] vmx_fpu_activate.part.61+0x45/0xb0 [kvm_intel]
        [<ffffffffa0461865>] vmx_fpu_activate+0x15/0x20 [kvm_intel]
        [<ffffffffa0560b91>] kvm_arch_vcpu_create+0x51/0x70 [kvm]
        [<ffffffffa0548011>] kvm_vm_ioctl+0x1c1/0x760 [kvm]
        [<ffffffff8118b55a>] ? handle_mm_fault+0x49a/0xec0
        [<ffffffff811e47d5>] do_vfs_ioctl+0x2e5/0x4c0
        [<ffffffff8127abbe>] ? file_has_perm+0xae/0xc0
        [<ffffffff811e4a51>] SyS_ioctl+0xa1/0xc0
        [<ffffffff81630949>] system_call_fastpath+0x16/0x1b
      
      (Note: we also unconditionally activate FPU in vmx_vcpu_reset(), so the
       removed code added nothing.)
      
      Fixes: c447e76b ("kvm/fpu: Enable eager restore kvm FPU for MPX")
      Cc: <stable@vger.kernel.org>
      Reported-by: NVlastimil Holer <vlastimil.holer@gmail.com>
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      370777da
    • P
      KVM: x86: reintroduce kvm_is_mmio_pfn · d1fe9219
      Paolo Bonzini 提交于
      The call to get_mt_mask was really using kvm_is_reserved_pfn to
      detect an MMIO-backed page.  In this case, we want "false" to be
      returned for the zero page.
      
      Reintroduce a separate kvm_is_mmio_pfn predicate for this use
      only.
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      d1fe9219
    • P
      x86: hyperv: add CPUID bit for crash handlers · 5d75a747
      Paolo Bonzini 提交于
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      5d75a747
    • R
      MIPS: O32: Use compat_sys_getsockopt. · 51d53674
      Ralf Baechle 提交于
      We were using the native syscall and that results in subtle breakage.
      
      This is the same issue as fixed in 077d0e65
      (MIPS: N32: Use compat getsockopt syscall) but that commit did fix it only
      for N32.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=100291
      51d53674
    • P
      MIPS: c-r4k: Extend way_string array · 1e18ac7a
      Paul Burton 提交于
      The L2 cache in the I6400 core has 16 ways, so extend the way_string
      array to take such caches into account.
      
      [ralf@linux-mips.org: Other already supported CPUs are free to support
      more than 8 ways of cache as well.]
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/10640/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1e18ac7a
    • J
      MIPS: Pistachio: Support CDMM & Fast Debug Channel · 6b5e741e
      James Hogan 提交于
      Implement the mips_cdmm_phys_base() platform callback to provide a
      default Common Device Memory Map (CDMM) physical base address for the
      Pistachio SoC. This allows the CDMM in each VPE to be configured and
      probed for devices, such as the Fast Debug Channel (FDC).
      
      The physical address chosen is just below the default CPC address, which
      appears to also be unallocated.
      
      The FDC IRQ is also usable on Pistachio, and is routed through the GIC,
      so implement the get_c0_fdc_int() platform callback using
      gic_get_c0_fdc_int(), so the FDC driver doesn't have to fall back to
      polling.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: James Hartley <james.hartley@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
      Patchwork: http://patchwork.linux-mips.org/patch/9749/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6b5e741e
    • J
      MIPS: Malta: Make GIC FDC IRQ workaround Malta specific · 6249ecbb
      James Hogan 提交于
      Wider testing reveals that the Fast Debug Channel (FDC) interrupt is
      routed through the GIC just fine on Pistachio SoC, even though it
      contains interAptiv cores. Clearly the FDC interrupt routing problems
      previously observed on interAptiv and proAptiv cores are specific to the
      Malta FPGA bitstreams.
      
      Move the workaround for interAptiv and proAptiv out of
      gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's
      get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use
      the FDC interrupt.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: linux-mips@linux-mips.org
      Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
      Cc: James Hartley <james.hartley@imgtec.com>
      Patchwork: http://patchwork.linux-mips.org/patch/9748/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6249ecbb
    • M
      MIPS: c-r4k: Fix cache flushing for MT cores · cccf34e9
      Markos Chandras 提交于
      MT_SMP is not the only SMP option for MT cores. The MT_SMP option
      allows more than one VPE per core to appear as a secondary CPU in the
      system. Because of how CM works, it propagates the address-based
      cache ops to the secondary cores but not the index-based ones.
      Because of that, the code does not use IPIs to flush the L1 caches on
      secondary cores because the CM would have done that already. However,
      the CM functionality is independent of the type of SMP kernel so even in
      non-MT kernels, IPIs are not necessary. As a result of which, we change
      the conditional to depend on the CM presence. Moreover, since VPEs on
      the same core share the same L1 caches, there is no need to send an
      IPI on all of them so we calculate a suitable cpumask with only one
      VPE per core.
      Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
      Cc: <stable@vger.kernel.org> # 3.15+
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/10654/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cccf34e9
    • Q
      intel_pmc_ipc: Update kerneldoc formatting · 02941007
      qipeng.zha 提交于
      Update kerneldoc formatting per Documentation/kernel-dec-nano-HOWTO.txt.
      Signed-off-by: Nqipeng.zha <qipeng.zha@intel.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      02941007
  4. 09 7月, 2015 7 次提交