clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: NThierry Reding <treding@nvidia.com>

There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>

Implement clock support for Tegra124.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 introduces a new PLL type, PLLSS. Add support for it.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move tegra20 to common tegra clock infrastructure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move tegra30 to common tegra clock infrastructure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce a common function which performs super clock initialization for
Tegra114 and beyond.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Add a common infra for registering clkdev. This allows decoupling clk
registration from clkdev registration.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce a common infrastructure for sharing clock initialization between
SoCs.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra30 clock bindings lack few IDs for audio and clk_out muxes.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Add spread spectrum control for PLLE in Tegra114.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock.  We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.
Signed-off-by: NAndrew Chew <achew@nvidia.com>
Signed-off-by: NMark Zhang <markz@nvidia.com>

Perform upwards rounding when calculating dividers for periph clks on Tegra30
and Tegra114.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.
Signed-off-by: NMark Zhang <markz@nvidia.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>

In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".

Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.
Signed-off-by: NMark Zhang <markz@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra114 sbc1-sbc6 have more possible parent clocks than Tegra30.
So correct the parents and mux width for them.
Signed-off-by: NMark Zhang <markz@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

As the clock IDs are now specified in a header file, we can use those
definitions instead of maintaining an internal enum.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>