- 06 11月, 2012 3 次提交
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由 Tero Kristo 提交于
These new structs will hold the sleep voltage levels (omap_vc_params) and voltage processor min / max voltages (omap_vp_params.) Previously these were part of the PMIC struct, but they do not really belong there, as they are OMAP chip specific, not PMIC specific parameters. voltdm code is also changed to use the new structs. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
These are now called vddmin and vddmax, as these fields will be used globally for selecting voltage ranges for a pmic channel, and not only for voltage processor. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Nishanth Menon 提交于
Every PMIC has it's own eccentricities, For example, one of the PMIC has MSB set to 1 for a specific function - voltage enable! using an hardcoded value specific for TWL when copied over to such an implementation causes the system to crash as the MSB bit was 0 and the voltage got disabled!. Instead we use actual values and depend on the convertion routines to abstract out the eccentricities of each PMIC. With this, we can now move the voltages to a common location in voltage.h as they are no longer dependent on PMICs and expect the PMIC's conversion routines to set a cap if the voltage is out of reach for the PMIC. Reported-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NVishwanath BS <vishwanath.bs@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 24 10月, 2012 1 次提交
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由 Vaibhav Hiremath 提交于
ARM: AM33XX: Fix configuration of dmtimer parent clock by dmtimer driverDate:Wed, 17 Oct 2012 13:55:55 -0500 Add dmtimer clock aliases for AM33XX devices so that the parent clock for the dmtimer can be set correctly by the dmtimer driver. Without these clock aliases the dmtimer driver will fail to find the parent clocks for the dmtimer. Verified that DMTIMERs can be successfully requested on AM335x beagle bone. Original patch was provided by Vaibhav Hiremath [1]. Changelog and additional verification performed by Jon Hunter. [1] http://marc.info/?l=linux-omap&m=134693631608018&w=2Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: NJon Hunter <jon-hunter@ti.com> Tested-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 10月, 2012 5 次提交
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由 Kevin Hilman 提交于
After commit 24d7b40a (ARM: OMAP2+: PM: MPU DVFS: use generic CPU device for MPU-SS), OPPs are registered using an existing CPU device, not the omap_device for MPU-SS. First, fix the board file to use get_cpu_device() as required by the above commit, otherwise custom OPPs will be added to the wrong device. Second, the board files OPP init is called from the its init_machine method, and the generic CPU devices are not yet created when init_machine is run. Therefore OPP initialization will fail. To fix, use a device_initcall() for the board file's OPP customization, and make the device_initcall board-specific by using a machine_is check. Reported-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tony Lindgren 提交于
On n900 uart1 pins are not not used for uart, instead they are used to connect to a cell modem over ssi. Looks like we're currently missing these signal names for 3430 for some reason, and only have some of them listed for 3630. Obviously the signals are there for 3430 if n900 is using them and they are documented in some TRMs. Note that these will eventually be replaced by device tree based pinctrl-single.c driver. But for now these are needed to verify the SSI pins for devices like Nokia N900. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Commit 8f31cefe (ARM: OMAP2+: select PINCTRL in Kconfig) added select PINCTRL, but accdentally added it to a wrong location. We want to select if for ARCH_OMAP2PLUS, not for ARCH_OMAP2PLUS_TYPICAL. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Kevin Hilman 提交于
The runtime PM framework assumes that the hardware state of devices when initialized is disabled. For all omap_devices, we idle/disable device by default. However, the console uart uses a "no idle" option during omap_device init in order to allow earlyprintk usage to work seamlessly during boot. Because the hardware is left partially enabled after init (whatever the bootloader settings were), the omap_device should later be fully initialized (including mux) and the runtime PM framework should be told that the device is active, and not disabled so that the hardware state is in sync with runtime PM state. To fix, after the device has been created/registered, call omap_device_enable() to finialize init and use pm_runtime_set_active() to tell the runtime PM core the device is enabled. Tested on 2420/n810, 3530/Overo, 3530/Beagle, 3730/OveroSTORM, 3730/Beagle-xM, 4460/PandaES. Suggested-by: NRussell King <rmk+kernel@arm.linux.org.uk> Cc: Felipe Balbi <balbi@ti.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Paul Walmsley 提交于
On OMAP34xx/35xx, and OMAP36xx chips with ES < 1.2, if the PER powerdomain goes to OSWR or OFF while CORE stays at CSWR or ON, or if, upon chip wakeup from OSWR or OFF, the CORE powerdomain goes ON before PER, the UART3/4 FIFOs and McBSP2/3 SIDETONE memories will be unusable. This is erratum i582 in the OMAP36xx Silicon Errata document. This patch implements one of several parts of the workaround: the addition of the wakeup dependency between the PER and WKUP clockdomains, such that PER will wake up at the same time CORE_L3 does. This is not a complete workaround. For it to be complete: 1. the PER powerdomain's next power state must not be set to OSWR or OFF if the CORE powerdomain's next power state is set to CSWR or ON; 2. the UART3/4 FIFO and McBSP2/3 SIDETONE loopback tests should be run if the LASTPOWERSTATEENTERED bits for PER and CORE indicate that PER went OFF while CORE stayed on. If loopback tests fail, then those devices will be unusable until PER and CORE can undergo a transition from ON to OSWR/OFF and back ON. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 18 10月, 2012 2 次提交
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由 Jon Hunter 提交于
Currently, if the GPMC driver fails to reserve memory when probed we will call BUG() and the kernel will not boot. Instead of calling BUG(), return an error from probe and allow kernel to boot. Boot tested on AM335x beagle bone board and OMAP4430 Panda board. V2 changes: - Ensure that clock and memory resources are released on error. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
Previously the code only acquired spinlock after increasing / decreasing the usecount value, which is wrong. This leaves a small window where a task switch may occur between the check of the usecount and the actual wakeup / sleep of the domain. Fixed by moving the spinlock locking before the usecount access. Left the usecount as atomic_t if someone wants an easy access to the parameter through atomic_read. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 17 10月, 2012 3 次提交
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由 Sebastien Guiriec 提交于
Correct DMIC hwmod lockup error message and replace printk() by pr_err(). Signed-off-by: NSebastien Guiriec <s-guiriec@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Benoit Cousson 提交于
The GPMC code has been converted to a driver by the following commit: commit da496873 Author: Afzal Mohammed <afzal@ti.com> Date: Sun Sep 23 17:28:25 2012 -0600 ARM: OMAP2+: gpmc: minimal driver support It now requests a clock with con-id "fck" otherwise the probe will fails. [ 0.342010] omap-gpmc omap-gpmc: error: clk_get [ 0.346771] omap-gpmc: probe of omap-gpmc failed with error -2 Add the "omap-gmpc" dev-id and fck con-id to the already existing gmpc-fck dummy clock. Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Afzal Mohammed <afzal@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Commit 7d7e1eba (ARM: OMAP2+: Prepare for irqs.h removal) changed the interrupts to allow enabling sparse IRQ, but accidentally added the omap3 INTC base to the local IRQ. This causes the following: twd: can't register interrupt 45 (-22) twd_local_timer_register failed -22 The right fix is to not add any base, as it is a local timer. For the OMAP44XX_IRQ_LOCALWDT we had defined earlier there are no users, so no need to fix that. Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 14 10月, 2012 1 次提交
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由 Russell King 提交于
As suggested by Andrew Morton: This is a pet peeve of mine. Any time there's a long list of items (header file inclusions, kconfig entries, array initalisers, etc) and someone wants to add a new item, they *always* go and stick it at the end of the list. Guys, don't do this. Either put the new item into a randomly-chosen position or, probably better, alphanumerically sort the list. lets sort all our select statements alphanumerically. This commit was created by the following perl: while (<>) { while (/\\\s*$/) { $_ .= <>; } undef %selects if /^\s*config\s+/; if (/^\s+select\s+(\w+).*/) { if (defined($selects{$1})) { if ($selects{$1} eq $_) { print STDERR "Warning: removing duplicated $1 entry\n"; } else { print STDERR "Error: $1 differently selected\n". "\tOld: $selects{$1}\n". "\tNew: $_\n"; exit 1; } } $selects{$1} = $_; next; } if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or /^endif/ or /^endchoice/)) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } undef %selects; } print; } if (%selects) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } } It found two duplicates: Warning: removing duplicated S5P_SETUP_MIPIPHY entry Warning: removing duplicated HARDIRQS_SW_RESEND entry and they are identical duplicates, hence the shrinkage in the diffstat of two lines. We have four testers reporting success of this change (Tony, Stephen, Linus and Sekhar.) Acked-by: NJason Cooper <jason@lakedaemon.net> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 10月, 2012 15 次提交
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由 Paul Walmsley 提交于
Commit eb05f691 ("ARM: OMAP: hwmod: partially un-reset hwmods might not be properly enabled") added code to skip the IP block disable sequence if all of the block's hardreset lines weren't asserted. But this did not handle the case when no hardreset lines were associated with a module, which is the general case. In that situation, the IP block disable would be skipped. This is likely to cause PM regressions. So, modify _omap4_disable_module() and _am33xx_disable_module() to only bail out early if there are any hardreset lines asserted. And move the AM33xx test above the actual module disable code to ensure that the behavior is consistent. Reported-by: NArchit Taneja <a0393947@ti.com> Tested-by: Archit Taneja <a0393947@ti.com> # DSS Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: NVaibhav Hiremath <hvaibhav@ti.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com> # AM335x Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jon Hunter 提交于
Commit b71c7217 (ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems) added a workaround for the EMU clock domain on OMAP3/4 devices to prevent the clock domain for transitioning while it is in use. In the proposed patch [1] code was added to the omap3xxx_clkdm_clk_enable() and omap3xxx_clkdm_clk_disable() functions to check for the flag CLKDM_MISSING_IDLE_REPORTING and perform the appropriate action. However, in the merged patch it appears that this code was added to the omap2_clkdm_clk_enable() and omap2_clkdm_clk_disable() functions by mistake. [1] http://marc.info/?l=linux-arm-kernel&m=134383567112518&w=2Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Vikram Narayanan 提交于
Use the enum for board_ref_clock from linux/wl12xx.h Signed-off-by: NVikram Narayanan <vikram186@gmail.com> Cc: linux-omap@vger.kernel.org Reviewed-by: Pankaj Jangra<jangra.pankaj9@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Wei Yongjun 提交于
Remove duplicated include. dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Senna Tschudin 提交于
Found by http://coccinelle.lip6.fr/Signed-off-by: NPeter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
u-boot stopped configuring 'non essential' pins recently. These pins are essential for audio and need to be done to have working audio on the board. Pin Mux configuration for: twl6040 audpwron gpio, McPDM, and McBSP1. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
u-boot stopped configuring 'non essential' pins recently. These pins are essential for audio and need to be done to have working audio on the board. Pin Mux configuration for: twl6040 audpwron gpio, McPDM, DMIC, McBSP1 and McBSP2. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Raphael Assenat 提交于
This patch adds a missing hwmod entry for the HDQ/1-Wire module present in the AM3505/17 CPUs. This restores 1-Wire support to our AM3505 boards. We think it probably stopped working with commit 96b1b29d ARM: OMAP2+: HDQ1W: use omap_device Signed-off-by: NRaphael Assenat <raph@8d.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Afzal Mohammed 提交于
compiler complained, `gpmc_remove' referenced in section `.data' of arch/arm/mach-omap2/built-in.o: defined in discarded section `.exit.text' of arch/arm/mach-omap2/built-in.o Annotate gpmc_remove function and dependents with __devexit. Reported-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NAfzal Mohammed <afzal@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Wei Yongjun 提交于
In case of error, the function clk_get() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Wei Yongjun 提交于
In case of error, the function omap_device_alloc() returns ERR_PTR() not NULL pointer. The NULL test in the return value check should be replaced with IS_ERR(). dpatch engine is used to auto generated this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Wei Yongjun 提交于
In case of error, the function omap_device_alloc() returns ERR_PTR() not NULL pointer. The NULL test in the return value check should be replaced with IS_ERR(). dpatch engine is used to auto generated this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Kevin Hilman 提交于
Currently, a dummy omap_device is created for the MPU sub-system so that a device node exists for MPU DVFS. Specifically, for the association of MPU OPPs to a device node, and so that a voltage regulator can be mapped to a device node. For drivers to get a handle to this device node, an OMAP-specific API has been used. However, the kernel already has device nodes for the CPU(s) in the system, so we can use those instead of an OMAP-specific dummy device and then drivers (like OMAP CPUfreq) can use generic APIs. To use the existing CPU device nodes, modify the OPP creation and regulator registration to use the CPU0 device node for registraion. NOTE: this patch always uses CPU0 as the device node. On all OMAPs today, MPU DVFS scales all CPUs together, so this will not be a problem, but this assumption will need to be changed if independently scalable CPUs are introduced. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Shubhrajyoti D 提交于
rx51_si4713_dev is referenced only from rx51_init_si4713. So the memory for rx51_si4713_dev can be safely freed after init. Also it references rx51_si4713_board_info which is __initdata_or_module. fixes the below warning. WARNING: vmlinux.o(.data+0x30958): Section mismatch in reference from the variable rx51_si4713_dev to the (unknown reference) .init.data:(unknown) The variable rx51_si4713_dev references the (unknown reference) __initdata (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NShubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 R Sricharan 提交于
memblock_steal tries to reserve physical memory during boot. When the requested size is not aligned on the section size then, the remaining memory available for lowmem becomes unaligned on the section boundary. There is a issue with this, which is discussed in the thread below. https://lkml.org/lkml/2012/6/28/112 The final conclusion from the thread seems to be align the memblock_steal calls on the SECTION boundary. The issue comes out when LPAE is enabled, where the section size is 2MB. Boot tested this on OMAP5 evm with and without LPAE. Signed-off-by: NR Sricharan <r.sricharan@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 08 10月, 2012 3 次提交
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由 Paul Walmsley 提交于
Commit e54adb1e ("ARM: OMAP: omap3evm: cleanup revision bits") adds a new sparse[1] warning: arch/arm/mach-omap2/board-omap3evm.c:90:4: warning: symbol 'get_omap3_evm_rev' was not declared. Should it be static? This symbol no longer appears to be used outside this file, so mark it static and remove the export. ... 1. https://sparse.wiki.kernel.org/index.php/Main_PageSigned-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tony Lindgren <tony@atomide.com>
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由 Jon Hunter 提交于
Commit 7d7e1eba (ARM: OMAP2+: Prepare for irqs.h removal) and commit ec2c0825 (ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ) updated the way interrupts for OMAP2/3 devices are defined in the HWMOD data structures to being an index plus a fixed offset (defined by OMAP_INTC_START). The definition of the PMU interrupts on OMAP2/3 devices is missing the OMAP_INTC_START offset and so this is causing the allocation of PMU interrupts to fail on OMAP2/3 devices. So add the offset to fix this. This is patch is based upon Tony's master branch for OMAP. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Vaibhav Hiremath 提交于
After Rajendra's common-clock preparation series, commit (a1978ef4da1 - ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage) the clkdev table need to update with an entry for clocks used by hwmod to have clock name same as the alias. Without this, the clk_get() in omap_hwmod would fail. Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 06 10月, 2012 1 次提交
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由 Andi Kleen 提交于
Signed-off-by: NAndi Kleen <ak@linux.intel.com> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 03 10月, 2012 3 次提交
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由 Wei Yongjun 提交于
In case of error, the function voltdm_lookup() returns NULL not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: NJean Pihet <j-pihet@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Wei Yongjun 提交于
In case of error, the function voltdm_lookup() returns NULL not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: NJean Pihet <j-pihet@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Wei Yongjun 提交于
In case of error, the function omap_device_get_by_hwmod_name() returns ERR_PTR() not NULL pointer. The NULL test in the return value check should be replaced with IS_ERR(). dpatch engine is used to auto generated this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 25 9月, 2012 1 次提交
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由 Peter Ujfalusi 提交于
On OMAP4 the i2c1 bus is dedicated for the PMIC and audio related devices. Manufacturers can opt to use different codec than twl6040 and also can add audio related IC to the bus (external amplifier for example on SDP4430). Make it possible to add different set of additional devices to i2c1 bus on OMAP4 boards. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> [tony@atomide.com: updated for removal of irqs.h] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 24 9月, 2012 2 次提交
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由 Jon Hunter 提交于
OMAP4460 and OMAP4470 devices have dedicated PMU interrupts and so add these interrupts to the MPU HWMOD so we can use these for PMU events on these devices. The PMU interrupts need to be the first interrupts in the array of interrupts as the ARM PMU driver assumes this. By using these dedicated interrupts we only need to enable the MPU and DEBUG sub-systems for PMU to work. This is different to OMAP4430 that did not have dedicated interrupts and required other power domains in addition to the DEBUG sub-system to be enabled so we could route the PMU events to the CTI interrupts. Hence, OMAP4460 and OMAP4470 devices can use the same list of HWMODs to create the PMU device that is using by OMAP3. Cc: Ming Lei <ming.lei@canonical.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: NJon Hunter <jon-hunter@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jon Hunter 提交于
The original implementation of this patch was done by Ming Lei for PMU on OMAP4 [1]. Since then the PM runtime calls have been moved into the ARM PMU code and this greatly simplifies the changes. The another differnce since the original version, is that it is no longer necessary to call pm_runtime_get/put during the PMU initialisation was we are no longer accessing the hardware at this stage. By adding runtime PM support, we can ensure that the appropriate power and clock domains are kept on while PMU is being used. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074153.html Cc: Ming Lei <ming.lei@canonical.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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