Add iio-hwmon node to expose the temperature channel on Vybrid as
hardware monitor device using the iio_hwmon driver.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Add a device tree node entry for DAC peripheral on Vybrid SoC.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

GPLv2-only devicetrees make reuse difficult for software components
licensed under a different license.

The consensus is that a GPL/X11 dual-license should allow all necessary
uses, so relicense the vfxxx.dtsi, vf500.dtsi and vf610.dtsi files to
this combination.

CCs were acquired using (updated some email addresses, commented out
bouncing email addresses with --):
git shortlog -sne --no-merges arch/arm/boot/dts/vf???.dtsi

--CC: Chao Fu <B44548@freescale.com>
CC: Cosmin Stoica <cosminstefan.stoica@freescale.com>
CC: Frank Li <Frank.Li@freescale.com>
CC: Fugang Duan <B38611@freescale.com>
--CC: Huang Shijie <b32955@freescale.com>
--CC: Jingchang Lu <jingchang.lu@freescale.com>
--CC: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: NSanchayan Maity <maitysanchayan@gmail.com>
Acked-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: NYuan Yao <yao.yuan@freescale.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add alias for FEC ethernet on Vybrid to allow bootloaders (like U-Boot)
patch-in the MAC address using this alias.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This adds the remaining SAI instances SAI0, SAI1 and SAI3. All
instances are very similar, except that the DMA channel of SAI3
is available on MUX1 (compared to MUX0 for SAI0-SAI2). Also,
SAI3 has a slightly different memory map due to a deeper FIFO,
however in practice the current driver works for SAI3 fine.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Extend the existing Vybrid DSPI devicetree implementation to also
describe the dspi2 and dspi3 functional blocks.
Signed-off-by: NCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

So far, only the bus clock has been assigned, but in reality the
SAI IP has for clock inputs. The driver has been updated to
make use of the additional clock inputs by c3ecef21 ("ASoC:
fsl_sai: add sai master mode support"). Due to a bug in the
clock tree, the audio clock has been enabled none the less by
the specified bus clock (see "ARM: imx: clk-vf610: fix SAI
clock tree"), which made master mode even without the proper
clock assigned working.

This patch completes the clock definition for SAI2. On Vybrid,
only two MCLK out of the four options are available (the first
being the bus clock itself). See chapter 8.10.1.2.3 of the
Vybrid Reference manual ("SAI transmitter and receiver options
for MCLK selection"). Note: The audio clocks are only required
in master mode.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Per the Vybrid Reference Manual (section 3.8.6.1), dspi0 has 6 chip
select signals associated with it, while dspi1 has only 4.
Signed-off-by: NCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Cc: <stable@vger.kernel.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Something seems to have gone wrong during the merging of the device
tree changes with the following patch

"ARM: dts: add property for maximum ADC clock frequencies"

The property "fsl,adck-max-frequency" instead of being applied for
the ADC1 node got applied to the esdhc0 node. This patch fixes it.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>
Fixes: def0641e ("ARM: dts: add property for maximum ADC clock frequencies")
Cc: <stable@vger.kernel.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This adds the NAND flash controller (NFC) peripherial. The driver
supports the SLC NAND chips found on Freescale's Vybrid Tower System
Module. The Micron NAND chip on the module needs 4-bit ECC per 512
byte page. Use 24-bit ECC per 2k page, which is supported by the
driver.
Signed-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
Reviewed-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The ADC clock frequency is limited depending on modes used. Add
device tree property which allow to set the mode used and the
maximum frequency ratings for the instance. These allows to
set the ADC clock to a frequency which is within specification
according to the actual mode used.
Acked-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This commit adds io-channel-cells property to the ADC node. This
property is required in order for an IIO consumer driver to work.
Especially required for Colibri VF50, as the touchscreen driver
uses ADC channels with the ADC driver based on IIO framework.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

snvs is MFP device. Change dts to use syscon to allocate register resource.
snvs power off also switch to common syscon-poweroff
Signed-off-by: NFrank Li <Frank.Li@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Extend the existing Vybrid eSDHC devicetree implementation to also
describe the esdhc0 functional block.

Tested on a custom VF610-based board with a Toshiba THGBM1G5D2EBAI7 eMMC
module attached to esdhc0.
Signed-off-by: NCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This commit extends the existing Vybrid QSPI devicetree implementation
to also describe the qspi1 functional block.
Signed-off-by: NCory Tusar <cory.tusar@pid1solutions.com>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Both 'reg' and 'reg-names' are required properties according to binding
documentation, and both should contain two items.
Signed-off-by: NCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This commit extends the existing Vybrid I2C support to cover buses i2c1,
i2c2, and i2c3.  Based in (very) large part on an initial patch by
Stefan Agner that was just lacking a couple of DMA assignments.
Signed-off-by: NCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

While adding the MSCM interrupt router, all interrupts have been moved
to vfxxx.dtsi again. However, some properties got lost. Readd the
missing interrupt properties.

Fixes: 97e6466ab9d0 ("ARM: dts: vf610: add Miscellaneous System Control
Module (MSCM)")
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.

In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The anyway depricated gpio-range-cells property was never used
by the pin controller driver. This patch removes it.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On Vybrid, all peripherals are numbered starting with zero,
including the GPIO and PORT module. However, the labels of the
corresponding device tree nodes start with one, which is confusing.
Fix that by renaming the labels of the gpio nodes in the device
tree.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add device tree node for the Secure Non-Volatile Storage
(SNVS) on the VF610 platform. The SNVS block also has a
Real Time Counter (RTC).
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the system reset controller (SRC) module and use syscon-reboot
to register a restart handler which restarts the SoC using the
SRC SW_RST bit.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

During restructuring of the device tree files the watchdog was
changed to be disabled by default. However, since the watchdog
instance is dedicated to the Cortex-A5, enable the peripheral
by default in the base device tree vf500.dtsi.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Use GPIO support by adding SD card detection configuration and
GPIO pinmux for Colibri's standard GPIO pins. Attach the GPIO
pins to the iomuxc node to get the GPIO pin settings applied.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This adds more generic base device trees for Vybrid SoCs. There
are three series of Vybrid SoC commonly available:
- VF3xx series: single core, Cortex-A5 without external memory
- VF5xx series: single core, Cortex-A5
- VF6xx series: dual core, Cortex-A5/Cortex-M4

The second digit represents the presents of a L2 cache (VFx1x).

The VF3xx series are not suitable for Linux especially since the
internal memory is quite small (1.5MiB).

The VF500 is essentially the base SoC, with only one core and
without L1 cache. The VF610 is a superset of the VF500, hence
vf500.dtsi is then included and enhanced by vf610.dtsi. There is
no board using VF510 or VF600 currently, but, if needed, they can
be added easily.

The Linux kernel can also run on the Cortex-M4 CPU of Vybrid
using !MMU support. This patchset creates a device tree structure
which allows to share peripherals nodes for a VF6xx Cortex-M4
device tree too. The two CPU types have different views of the
system: Foremost they are using different interrupt controllers,
but also the memory map is slightly different. The base device
tree vfxxx.dtsi allows to create SoC and board level device trees
supporting the Cortex-M4 while reusing the shared peripherals
nodes.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The clock controller module (CCM) has several clock inputs, which
are connected to external crystal oscillators. To reflect this,
assign these fixed clocks to the CCM node directly.

This especially resolves initialization order dependencies we had
with the earlier initialization code: When resolving of the fixed
clocks failed in clk-vf610, the code created fixed clocks with a
rate of 0.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add Global Timer support which is part of the private peripherals
of the Cortex-A5 processor. This Global Timer is compatible with the
Cortex-A9 implementation. It's a 64-bit timer and is clocked by the
peripheral clock, which is typically 133 or 166MHz on Vybrid.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Acked-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add device tree node for usbmisc which controls the non-core USB
registers. This is required to use the property to disable the over-
current detection.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This adds USB PHY and USB controller nodes. Vybrid SoCs have two
independent USB cores which each supports DR (dual role). However,
real OTG is not supported since the OTG ID pin is not available.

The PHYs are located within the anadig register range, hence we need
to change the length of the anadig registers.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add FlexCAN node for the two FlexCAN IP instances in Vybrid.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This adds devicetree node for VF610, and there are 8 channels
supported.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NYuan Yao <yao.yuan@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The kernel was not able to boot from SD card because sdhc support
was not present into the dts.

A new entry for sdhc1 was added for vf610-twr board based on the
compatible entry present on imx53.

After applying these changes, the kernel is able to boot successfully
from SD card.
Signed-off-by: NCosmin Stoica <cosminstefan.stoica@freescale.com>
Signed-off-by: NChircu Bogdan <Bogdan.Chircu@freescale.com>
Signed-off-by: NEddy Petrisor <eddy.petrisor@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Per bindings of fixed-clock, #clock-cells is a required property.  Let's
add it for those fixed rate clocks.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This is likely a copy-and-paste error from the
ARM GIC documentation, that has already been fixed.

address-cells should have been set to 0, as with the size
cells. As having those properties set to 0 is the
same thing as not specifying them, drop them completely.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add i2c dts node properties for eDMA support, them depend on the eDMA driver.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>