1. 11 6月, 2009 6 次提交
  2. 10 6月, 2009 1 次提交
  3. 06 6月, 2009 1 次提交
    • I
      perf_counter: Separate out attr->type from attr->config · a21ca2ca
      Ingo Molnar 提交于
      Counter type is a frequently used value and we do a lot of
      bit juggling by encoding and decoding it from attr->config.
      
      Clean this up by creating a separate attr->type field.
      
      Also clean up the various similarly complex user-space bits
      all around counter attribute management.
      
      The net improvement is significant, and it will be easier
      to add a new major type (which is what triggered this cleanup).
      
      (This changes the ABI, all tools are adapted.)
      (PowerPC build-tested.)
      
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a21ca2ca
  4. 04 6月, 2009 1 次提交
  5. 03 6月, 2009 4 次提交
    • P
      perf_counter: powerpc: Fix race causing "oops trying to read PMC0" errors · dcd945e0
      Paul Mackerras 提交于
      When using interrupting counters and limited (non-interrupting)
      counters at the same time, it's possible that we get an
      interrupt in write_mmcr0() after writing MMCR0 but before we
      have set up the counters using limited PMCs.  What happens then
      is that we get into perf_counter_interrupt() with
      counter->hw.idx = 0 for the limited counters, leading to the
      "oops trying to read PMC0" error message being printed.
      
      This fixes the problem by making perf_counter_interrupt()
      robust against counter->hw.idx being zero (the counter is just
      ignored in that case) and also by changing write_mmcr0() to
      write MMCR0 initially with the counter overflow interrupt
      enable bits masked (set to 0).  If the MMCR0 value requested by
      the caller has either of those bits set, we write MMCR0 again
      with the requested value of those bits after setting up the
      limited counters properly.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: John Kacur <jkacur@redhat.com>
      Cc: Stephane Eranian <eranian@googlemail.com>
      LKML-Reference: <18982.17684.138182.954599@cargo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      dcd945e0
    • P
      perf_counter: powerpc: Fix event alternative code generation on POWER5/5+ · 6984efb6
      Paul Mackerras 提交于
      Commit ef923214 ("perf_counter: powerpc: use u64 for event
      codes internally") introduced a bug where the return value from
      function find_alternative_bdecode gets put into a u64 variable
      and later tested to see if it is < 0.  The effect is that we
      get extra, bogus event code alternatives on POWER5 and POWER5+,
      leading to error messages such as "oops compute_mmcr failed"
      being printed and counters not counting properly.
      
      This fixes it by using s64 for the return type of
      find_alternative_bdecode and for the local variable that the
      caller puts the value in.  It also makes the event argument a
      u64 on POWER5+ for consistency.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: John Kacur <jkacur@redhat.com>
      Cc: Stephane Eranian <eranian@googlemail.com>
      LKML-Reference: <18982.17586.666132.90983@cargo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6984efb6
    • P
      perf_counter: Rename perf_counter_hw_event => perf_counter_attr · 0d48696f
      Peter Zijlstra 提交于
      The structure isn't hw only and when I read event, I think about those
      things that fall out the other end. Rename the thing.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: John Kacur <jkacur@redhat.com>
      Cc: Stephane Eranian <eranian@googlemail.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      0d48696f
    • P
      perf_counter: Rename various fields · b23f3325
      Peter Zijlstra 提交于
      A few renames:
      
        s/irq_period/sample_period/
        s/irq_freq/sample_freq/
        s/PERF_RECORD_/PERF_SAMPLE_/
        s/record_type/sample_type/
      
      And change both the new sample_type and read_format to u64.
      Reported-by: NStephane Eranian <eranian@googlemail.com>
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: John Kacur <jkacur@redhat.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      b23f3325
  6. 02 6月, 2009 1 次提交
  7. 27 5月, 2009 4 次提交
  8. 26 5月, 2009 2 次提交
    • P
      perf_counter: powerpc: Implement interrupt throttling · 8a7b8cb9
      Paul Mackerras 提交于
      This implements interrupt throttling on powerpc.  Since we don't have
      individual count enable/disable or interrupt enable/disable controls
      per counter, this simply sets the hardware counter to 0, meaning that
      it will not interrupt again until it has counted 2^31 counts, which
      will take at least 2^30 cycles assuming a maximum of 2 counts per
      cycle.  Also, we set counter->hw.period_left to the maximum possible
      value (2^63 - 1), so we won't report overflows for this counter for
      the forseeable future.
      
      The unthrottle operation restores counter->hw.period_left and the
      hardware counter so that we will once again report a counter overflow
      after counter->hw.irq_period counts.
      
      [ Impact: new perfcounters robustness feature on PowerPC ]
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      LKML-Reference: <18971.35823.643362.446774@cargo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8a7b8cb9
    • H
      powerpc/mm: Fix broken MMU PID stealing on !SMP · 8e35961b
      Hideo Saito 提交于
      The recent rework of the MMU PID handling for non-hash CPUs has a
      subtle bug in the !SMP "optimized" variant of the PID stealing
      function.  It clears the PID in the mm context before it calls
      local_flush_tlb_mm(). However, the later will not flush anything
      if the PID in the context is clear...
      Signed-off-by: NHideo Saito <hsaito.ppc@gmail.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8e35961b
  9. 23 5月, 2009 1 次提交
  10. 22 5月, 2009 1 次提交
  11. 18 5月, 2009 6 次提交
    • P
      perf_counter: powerpc: initialize cpuhw pointer before use · c0daaf3f
      Paul Mackerras 提交于
      Commit 9e35ad38 ("perf_counter: Rework the perf counter
      disable/enable") added code to the powerpc hw_perf_enable (renamed
      from hw_perf_restore) to test cpuhw->disabled and return immediately
      if it is not set (i.e. if the PMU is already enabled).
      
      Unfortunately the test got added before cpuhw was initialized,
      resulting in an oops the first time hw_perf_enable got called.
      This fixes it by moving the initialization of cpuhw to before
      cpuhw->disabled is tested.
      
      [ Impact: fix oops-causing bug on powerpc ]
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      LKML-Reference: <18960.56772.869734.304631@drongo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c0daaf3f
    • B
      powerpc: Explicit alignment for .data.cacheline_aligned · 0e337b42
      Benjamin Herrenschmidt 提交于
      I don't think anything guarantees that the objects in data.page_aligned
      are a multiple of PAGE_SIZE, thus the section may end on any boundary.
      
      So the following section, .data.cacheline_aligned needs an explicit
      alignment.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      0e337b42
    • G
      powerpc/ps3: Update ps3_defconfig · dc892288
      Geoff Levand 提交于
      Refresh and set these options:
      
       CONFIG_SYSFS_DEPRECATED_V2: y -> n
       CONFIG_INPUT_JOYSTICK:      y -> n
       CONFIG_HID_SONY:            n -> m
       CONFIG_RTC_DRV_PS3:         - -> m
      Signed-off-by: NGeoff Levand <geoffrey.levand@am.sony.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      dc892288
    • S
      powerpc/ftrace: Fix constraint to be early clobber · c3cf8667
      Steven Rostedt 提交于
      After upgrading my distcc boxes from gcc 4.2.2 to 4.4.0, the function
      graph tracer broke. This was discovered on my x86 boxes.
      
      The issue is that gcc used the same register for an output as it did for
      an input in an asm statement. I first thought this was a bug in gcc and
      reported it. I was notified that gcc was correct and that the output had
      to be flagged as an "early clobber".
      
      I noticed that powerpc had the same issue and this patch fixes it.
      Signed-off-by: NSteven Rostedt <rostedt@goodmis.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      c3cf8667
    • M
      powerpc/ftrace: Use pr_devel() in ftrace.c · 021376a3
      Michael Ellerman 提交于
      pr_debug() can now result in code being generated even when #DEBUG
      is not defined. That's not really desirable in the ftrace code
      which we want to be snappy.
      
      With CONFIG_DYNAMIC_DEBUG=y:
      
      size before:
         text	   data	    bss	    dec	    hex	filename
         3334	    672	      4	   4010	    faa	arch/powerpc/kernel/ftrace.o
      
      size after:
         text	   data	    bss	    dec	    hex	filename
         2616	    360	      4	   2980	    ba4	arch/powerpc/kernel/ftrace.o
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Acked-by: NSteven Rostedt <rostedt@goodmis.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      021376a3
    • M
      powerpc: Do not assert pte_locked for hugepage PTE entries · af3e4aca
      Mel Gorman 提交于
      With CONFIG_DEBUG_VM, an assertion is made when changing the protection
      flags of a PTE that the PTE is locked. Huge pages use a different pagetable
      format and the assertion is bogus and will always trigger with a bug looking
      something like
      
       Unable to handle kernel paging request for data at address 0xf1a00235800006f8
       Faulting instruction address: 0xc000000000034a80
       Oops: Kernel access of bad area, sig: 11 [#1]
       SMP NR_CPUS=32 NUMA Maple
       Modules linked in: dm_snapshot dm_mirror dm_region_hash
        dm_log dm_mod loop evdev ext3 jbd mbcache sg sd_mod ide_pci_generic
        pata_amd ata_generic ipr libata tg3 libphy scsi_mod windfarm_pid
        windfarm_smu_sat windfarm_max6690_sensor windfarm_lm75_sensor
        windfarm_cpufreq_clamp windfarm_core i2c_powermac
       NIP: c000000000034a80 LR: c000000000034b18 CTR: 0000000000000003
       REGS: c000000003037600 TRAP: 0300   Not tainted (2.6.30-rc3-autokern1)
       MSR: 9000000000009032 <EE,ME,IR,DR>  CR: 28002484  XER: 200fffff
       DAR: f1a00235800006f8, DSISR: 0000000040010000
       TASK = c0000002e54cc740[2960] 'map_high_trunca' THREAD: c000000003034000 CPU: 2
       GPR00: 4000000000000000 c000000003037880 c000000000895d30 c0000002e5a2e500
       GPR04: 00000000a0000000 c0000002edc40880 0000005700000393 0000000000000001
       GPR08: f000000011ac0000 01a00235800006e8 00000000000000f5 f1a00235800006e8
       GPR12: 0000000028000484 c0000000008dd780 0000000000001000 0000000000000000
       GPR16: fffffffffffff000 0000000000000000 00000000a0000000 c000000003037a20
       GPR20: c0000002e5f4ece8 0000000000001000 c0000002edc40880 0000000000000000
       GPR24: c0000002e5f4ece8 0000000000000000 00000000a0000000 c0000002e5f4ece8
       GPR28: 0000005700000393 c0000002e5a2e500 00000000a0000000 c000000003037880
       NIP [c000000000034a80] .assert_pte_locked+0xa4/0xd0
       LR [c000000000034b18] .ptep_set_access_flags+0x6c/0xb4
       Call Trace:
       [c000000003037880] [c000000003037990] 0xc000000003037990 (unreliable)
       [c000000003037910] [c000000000034b18] .ptep_set_access_flags+0x6c/0xb4
       [c0000000030379b0] [c00000000014bef8] .hugetlb_cow+0x124/0x674
       [c000000003037b00] [c00000000014c930] .hugetlb_fault+0x4e8/0x6f8
       [c000000003037c00] [c00000000013443c] .handle_mm_fault+0xac/0x828
       [c000000003037cf0] [c0000000000340a8] .do_page_fault+0x39c/0x584
       [c000000003037e30] [c0000000000057b0] handle_page_fault+0x20/0x5c
       Instruction dump:
       7d29582a 7d200074 7800d182 0b000000 3c004000 3960ffff 780007c6 796b00c4
       7d290214 7929a302 1d290068 7d6b4a14 <800b0010> 7c000074 7800d182 0b000000
      
      This patch fixes the problem by not asseting the PTE is locked for VMAs
      backed by huge pages.
      Signed-off-by: NMel Gorman <mel@csn.ul.ie>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      af3e4aca
  12. 15 5月, 2009 12 次提交
    • P
      perf_counter: powerpc: supply more precise information on counter overflow events · 0bbd0d4b
      Paul Mackerras 提交于
      This uses values from the MMCRA, SIAR and SDAR registers on
      powerpc to supply more precise information for overflow events,
      including a data address when PERF_RECORD_ADDR is specified.
      
      Since POWER6 uses different bit positions in MMCRA from earlier
      processors, this converts the struct power_pmu limited_pmc5_6
      field, which only had 0/1 values, into a flags field and
      defines bit values for its previous use (PPMU_LIMITED_PMC5_6)
      and a new flag (PPMU_ALT_SIPR) to indicate that the processor
      uses the POWER6 bit positions rather than the earlier
      positions.  It also adds definitions in reg.h for the new and
      old positions of the bit that indicates that the SIAR and SDAR
      values come from the same instruction.
      
      For the data address, the SDAR value is supplied if we are not
      doing instruction sampling.  In that case there is no guarantee
      that the address given in the PERF_RECORD_ADDR subrecord will
      correspond to the instruction whose address is given in the
      PERF_RECORD_IP subrecord.
      
      If instruction sampling is enabled (e.g. because this counter
      is counting a marked instruction event), then we only supply
      the SDAR value for the PERF_RECORD_ADDR subrecord if it
      corresponds to the instruction whose address is in the
      PERF_RECORD_IP subrecord.  Otherwise we supply 0.
      
      [ Impact: support more PMU hardware features on PowerPC ]
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Acked-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      LKML-Reference: <18955.37028.48861.555309@drongo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      0bbd0d4b
    • P
      perf_counter: powerpc: use u64 for event codes internally · ef923214
      Paul Mackerras 提交于
      Although the perf_counter API allows 63-bit raw event codes,
      internally in the powerpc back-end we had been using 32-bit
      event codes.  This expands them to 64 bits so that we can add
      bits for specifying threshold start/stop events and instruction
      sampling modes later.
      
      This also corrects the return value of can_go_on_limited_pmc;
      we were returning an event code rather than just a 0/1 value in
      some circumstances. That didn't particularly matter while event
      codes were 32-bit, but now that event codes are 64-bit it
      might, so this fixes it.
      
      [ Impact: extend PowerPC perfcounter interfaces from u32 to u64 ]
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Acked-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      LKML-Reference: <18955.36874.472452.353104@drongo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ef923214
    • P
      perf_counter: frequency based adaptive irq_period · 60db5e09
      Peter Zijlstra 提交于
      Instead of specifying the irq_period for a counter, provide a target interrupt
      frequency and dynamically adapt the irq_period to match this frequency.
      
      [ Impact: new perf-counter attribute/feature ]
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      LKML-Reference: <20090515132018.646195868@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      60db5e09
    • P
      perf_counter: Rework the perf counter disable/enable · 9e35ad38
      Peter Zijlstra 提交于
      The current disable/enable mechanism is:
      
      	token = hw_perf_save_disable();
      	...
      	/* do bits */
      	...
      	hw_perf_restore(token);
      
      This works well, provided that the use nests properly. Except we don't.
      
      x86 NMI/INT throttling has non-nested use of this, breaking things. Therefore
      provide a reference counter disable/enable interface, where the first disable
      disables the hardware, and the last enable enables the hardware again.
      
      [ Impact: refactor, simplify the PMU disable/enable logic ]
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      9e35ad38
    • B
      powerpc: Fix PCI ROM access · ad892a63
      Benjamin Herrenschmidt 提交于
      A couple of issues crept in since about 2.6.27 related to accessing PCI
      device ROMs on various powerpc machines.
      
      First, historically, we don't allocate the ROM resource in the resource
      tree. I'm not entirely certain of why, I susepct they often contained
      garbage on x86 but it's hard to tell. This causes the current generic
      code to always call pci_assign_resource() when trying to access the said
      ROM from sysfs, which will try to re-assign some new address regardless
      of what the ROM BAR was already set to at boot time. This can be a
      problem on hypervisor platforms like pSeries where we aren't supposed
      to move PCI devices around (and in fact probably can't).
      
      Second, our code that generates the PCI tree from the OF device-tree
      (instead of doing config space probing) which we mostly use on pseries
      at the moment, didn't set the (new) flag IORESOURCE_SIZEALIGN on any
      resource. That means that any attempt at re-assigning such a resource
      with pci_assign_resource() would fail due to resource_alignment()
      returning 0.
      
      This fixes this by doing these two things:
      
       - The code that calculates resource flags based on the OF device-node
      is improved to set IORESOURCE_SIZEALIGN on any valid BAR, and while at
      it also set IORESOURCE_READONLY for ROMs since we were lacking that too
      
       - We now allocate ROM resources as part of the resource tree. However
      to limit the chances of nasty conflicts due to busted firmwares, we
      only do it on the second pass of our two-passes allocation scheme,
      so that all valid and enabled BARs get precedence.
      
      This brings pSeries back the ability to access PCI ROMs via sysfs (and
      thus initialize various video cards from X etc...).
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ad892a63
    • B
      powerpc/pseries: Really fix the oprofile CPU type on pseries · b173f03d
      Benjamin Herrenschmidt 提交于
      My previous pach for fixing the oprofile CPU type got somewhat mismerged
      (by my fault) when it collided with another related patch. This should
      finally (fingers crossed) fix the whole thing.
      
      We make sure we keep the -old- oprofile type and CPU type whenever
      one of them was specified in the first pass through the function.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      b173f03d
    • G
      powerpc/cell: Make ptcal more reliable · 37cd8ed9
      Gerhard Stenzel 提交于
      There have been a series of checkstops on QS21 related to
      ptcal being set up incorrectly. On systems that only
      have memory on a single node, ptcal fails when it gets
      a pointer to memory on the remote node.
      
      Moreover, agressive prefetching in memcpy and other
      functions may accidentally touch the first cache line
      of the page that we reserve for ptcal, which causes
      an ECC checkstop.
      
      We now allocate pages only from the specified node, moves the
      ptcal area into the middle of the allocated page to avoid
      potential prefetch problems and prints the address of the
      ptcal area to facilitate diagnostics.
      Signed-off-by: NGerhard Stenzel <gerhard.stenzel@de.ibm.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      37cd8ed9
    • B
      powerpc: Allow mem=x cmdline to work with 4G+ · 49a84965
      Becky Bruce 提交于
      We're currently choking on mem=4g (and above) due to memory_limit
      being specified as an unsigned long. Make memory_limit
      phys_addr_t to fix this.
      Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      49a84965
    • K
      powerpc/mpic: Fix incorrect allocation of interrupt rev-map · 31207dab
      Kumar Gala 提交于
      Before when we were setting up the irq host map for mpic we passed in
      just isu_size for the size of the linear map.  However, for a number of
      mpic implementations we have no isu (thus pass in 0) and will end up
      with a no linear map (size = 0).  This causes us to always call
      irq_find_mapping() from mpic_get_irq().
      
      By moving the allocation of the host map to after we've determined the
      number of sources we can actually benefit from having a linear map for
      the non-isu users that covers all the interrupt sources.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      31207dab
    • M
      powerpc: Fix oprofile sampling of marked events on POWER7 · e5fc948b
      Maynard Johnson 提交于
      Description
      -----------
      Change ppc64 oprofile kernel driver to use the SLOT bits (MMCRA[37:39]only on
      older processors where those bits are defined.
      
      Background
      ----------
      The performance monitor unit of the 64-bit POWER processor family has the
      ability to collect accurate instruction-level samples when profiling on marked
      events (i.e., "PM_MRK_<event-name>").  In processors prior to POWER6, the MMCRA
      register contained "slot information" that the oprofile kernel driver used to
      adjust the value latched in the SIAR at the time of a PMU interrupt.  But as of
      POWER6, these slot bits in MMCRA are no longer necessary for oprofile to use,
      since the SIAR itself holds the accurate sampled instruction address.  With
      POWER6, these MMCRA slot bits were zero'ed out by hardware so oprofile's use of
      these slot bits was, in effect, a NOP.  But with POWER7, these bits are no
      longer zero'ed out; however, they serve some other purpose rather than slot
      information.  Thus, using these bits on POWER7 to adjust the SIAR value results
      in samples being attributed to the wrong instructions.  The attached patch
      changes the oprofile kernel driver to ignore these slot bits on all newer
      processors starting with POWER6.
      Signed-off-by: NMaynard Johnson <maynardj@us.ibm.com>
      Signed-off-by: NMichael Wolf <mjw@linux.vnet.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      e5fc948b
    • S
      powerpc/iseries: Fix pci breakage due to bad dma_data initialization · 397717c5
      Stephen Rothwell x 提交于
      Commit 4fc665b8 "powerpc: Merge 32 and
      64-bit dma code" made changes to the PCI initialisation code that added
      an assignment to archdata.dma_data but only for 32 bit code.  Commit
      7eef440a "powerpc/pci: Cosmetic cleanups
      of pci-common.c" removed the conditional compilation.  Unfortunately,
      the iSeries code setup the archdata.dma_data before that assignment was
      done - effectively overwriting the dma_data with NULL.
      
      Fix this up by moving the iSeries setup of dma_data into a
      pci_dma_dev_setup callback.
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      397717c5
    • T
      powerpc: Fix mktree build error on Mac OS X host · 93f1cc60
      Timur Tabi 提交于
      The mktree utility defines some variables as "uint", although this is not a
      standard C type, and so cross-compiling on Mac OS X fails.  Change this to
      "unsigned int".
      Signed-off-by: NTimur Tabi <timur@freescale.com>
      Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      93f1cc60