1. 24 2月, 2010 1 次提交
  2. 23 2月, 2010 13 次提交
  3. 29 1月, 2010 1 次提交
  4. 05 1月, 2010 1 次提交
    • R
      PCI/PM: Use per-device D3 delays · 1ae861e6
      Rafael J. Wysocki 提交于
      It turns out that some PCI devices require extra delays when changing
      power state from D3 to D0 (and the other way around).  Although this
      is against the PCI specification, we can handle it quite easily by
      allowing drivers to define arbitrary D3 delays for devices known to
      require extra time for switching power states.
      
      Introduce additional field d3_delay in struct pci_dev and use it to
      store the value of the device's D0->D3 delay, in miliseconds.  Make
      the PCI PM core code use the per-device d3_delay unless
      pci_pm_d3_delay is greater (in which case the latter is used).
      [This also allows the driver to specify d3_delay shorter than the
       10 ms required by the PCI standard if the device is known to be able
       to handle that.]
      
      Make the sky2 driver set d3_delay to 150 for devices handled by it.
      
      Fixes http://bugzilla.kernel.org/show_bug.cgi?id=14730 which is a
      listed regression from 2.6.30.
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      1ae861e6
  5. 17 12月, 2009 1 次提交
    • B
      PCI/cardbus: Add a fixup hook and fix powerpc · 2d1c8618
      Benjamin Herrenschmidt 提交于
      The cardbus code creates PCI devices without ever going through the
      necessary fixup bits and pieces that normal PCI devices go through.
      
      There's in fact a commented out call to pcibios_fixup_bus() in there,
      it's commented because ... it doesn't work.
      
      I could make pcibios_fixup_bus() do the right thing on powerpc easily
      but I felt it cleaner instead to provide a specific hook pci_fixup_cardbus
      for which a weak empty implementation is provided by the PCI core.
      
      This fixes cardbus on powerbooks and probably all other PowerPC
      platforms which was broken completely for ever on some platforms and
      since 2.6.31 on others such as PowerBooks when we made the DMA ops
      mandatory (since those are setup by the fixups).
      Acked-by: NDominik Brodowski <linux@dominikbrodowski.net>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      2d1c8618
  6. 15 12月, 2009 1 次提交
    • D
      PCI: Global variable decls must match the defs in section attributes · 491424c0
      David Howells 提交于
      Global variable declarations must match the definitions in section attributes
      as the compiler is at liberty to vary the method it uses to access a variable,
      depending on the section it is in.
      
      When building the FRV arch, I now see:
      
        drivers/built-in.o: In function `pci_apply_final_quirks':
        drivers/pci/quirks.c:2606: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size' defined in .devinit.data section in drivers/built-in.o
        drivers/pci/quirks.c:2623: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size' defined in .devinit.data section in drivers/built-in.o
        drivers/pci/quirks.c:2630: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size' defined in .devinit.data section in drivers/built-in.o
      
      because the declaration of pci_dfl_cache_line_size in linux/pci.h does not
      match the definition in drivers/pci/pci.c.
      Signed-off-by: NDavid Howells <dhowells@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      491424c0
  7. 05 12月, 2009 1 次提交
    • C
      PCI: add pci_request_acs · 5d990b62
      Chris Wright 提交于
      Commit ae21ee65 "PCI: acs p2p upsteram
      forwarding enabling" doesn't actually enable ACS.
      
      Add a function to pci core to allow an IOMMU to request that ACS
      be enabled.  The existing mechanism of using iommu_found() in the pci
      core to know when ACS should be enabled doesn't actually work due to
      initialization order;  iommu has only been detected not initialized.
      
      Have Intel and AMD IOMMUs request ACS, and Xen does as well during early
      init of dom0.
      
      Cc: Allen Kay <allen.m.kay@intel.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Joerg Roedel <joerg.roedel@amd.com>
      Signed-off-by: NChris Wright <chrisw@sous-sol.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      5d990b62
  8. 25 11月, 2009 2 次提交
  9. 07 11月, 2009 1 次提交
  10. 05 11月, 2009 4 次提交
    • A
      PCI: add pci_get_domain_bus_and_slot function · 3c299dc2
      Andrew Patterson 提交于
      Added the pci_get_domain_and_slot_function which is analogous to
      pci_get_bus_and_slot. It returns a pci_dev given a domain (segment) number,
      bus number, and devnr. Like pci_get_bus_and_slot,
      pci_get_domain_bus_and_slot holds a reference to the returned pci_dev.
      
      Converted pci_get_bus_and_slot to a wrapper that calls
      pci_get_domain_bus_and_slot with the domain hard-coded to 0.
      
      This routine was patterned off code suggested by Bjorn Helgaas.
      Acked-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      3c299dc2
    • M
      PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode · 05843961
      Matt Domsch 提交于
      Feedback from Hidetoshi Seto and Kenji Kaneshige incorporated.  This
      correctly handles PCI-X bridges, PCIe root ports and endpoints, and
      prints debug messages when invalid/reserved types are found in the
      HEST.  PCI devices not in domain/segment 0 are not represented in
      HEST, thus will be ignored.
      
      Today, the PCIe Advanced Error Reporting (AER) driver attaches itself
      to every PCIe root port for which BIOS reports it should, via ACPI
      _OSC.
      
      However, _OSC alone is insufficient for newer BIOSes.  Part of ACPI
      4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way
      for OS and BIOS to handshake over which errors for which components
      each will handle.  One table in ACPI 4.0 is the Hardware Error Source
      Table (HEST), where BIOS can define that errors for certain PCIe
      devices (or all devices), should be handled by BIOS ("Firmware First
      mode"), rather than be handled by the OS.
      
      Dell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so
      that it may manage such errors, log them to the System Event Log, and
      possibly take other actions.  The aer driver should honor this, and
      not attach itself to devices noted as such.
      
      Furthermore, Kenji Kaneshige reminded us to disallow changing the AER
      registers when respecting Firmware First mode.  Platform firmware is
      expected to manage these, and if changes to them are allowed, it could
      break that firmware's behavior.
      
      The HEST parsing code may be replaced in the future by a more
      feature-rich implementation.  This patch provides the minimum needed
      to prevent breakage until that implementation is available.
      Reviewed-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Reviewed-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NMatt Domsch <Matt_Domsch@dell.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      05843961
    • T
      pccard: configure CLS on attach · 15ea76d4
      Tejun Heo 提交于
      For non hotplug PCI devices, the system firmware usually configures
      CLS correctly.  For pccard devices system firmware can't do it and
      Linux PCI layer doesn't do it either.  Unfortunately this leads to
      poor performance for certain devices (sata_sil).  Unless MWI, which
      requires separate configuration, is to be used, CLS doesn't affect
      correctness, so the configuration should be harmless.
      
      This patch makes pci_set_cacheline_size() always built and export it
      and make pccard call it during attach.
      
      Please note that some other PCI hotplug drivers (shpchp and pciehp)
      also configure CLS on hotplug.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Daniel Ritz <daniel.ritz@gmx.ch>
      Cc: Dominik Brodowski <linux@dominikbrodowski.net>
      Cc: Greg KH <greg@kroah.com>
      Cc: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Cc: Axel Birndt <towerlexa@gmx.de>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      15ea76d4
    • J
      PCI: determine CLS more intelligently · ac1aa47b
      Jesse Barnes 提交于
      Till now, CLS has been determined either by arch code or as
      L1_CACHE_BYTES.  Only x86 and ia64 set CLS explicitly and x86 doesn't
      always get it right.  On most configurations, the chance is that
      firmware configures the correct value during boot.
      
      This patch makes pci_init() determine CLS by looking at what firmware
      has configured.  It scans all devices and if all non-zero values
      agree, the value is used.  If none is configured or there is a
      disagreement, pci_dfl_cache_line_size is used.  arch can set the dfl
      value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or
      override the actual one.
      
      ia64, x86 and sparc64 updated to set the default cls instead of the
      actual one.
      
      While at it, declare pci_cache_line_size and pci_dfl_cache_line_size
      in pci.h and drop private declarations from arch code.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NDavid Miller <davem@davemloft.net>
      Acked-by: NGreg KH <gregkh@suse.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      ac1aa47b
  11. 10 9月, 2009 6 次提交
  12. 30 6月, 2009 1 次提交
  13. 17 6月, 2009 5 次提交
  14. 16 6月, 2009 1 次提交
  15. 12 6月, 2009 1 次提交
    • A
      PCI: Add support for turning PCIe ECRC on or off · 43c16408
      Andrew Patterson 提交于
      Adds support for PCI Express transaction layer end-to-end CRC checking
      (ECRC).  This patch will enable/disable ECRC checking by setting/clearing
      the ECRC Check Enable and/or ECRC Generation Enable bits for devices that
      support ECRC.
      
      The ECRC setting is controlled by the "pci=ecrc=<policy>" command-line
      option. If this option is not set or is set to 'bios", the enable and
      generation bits are left in whatever state that firmware/BIOS set them to.
      The "off" setting turns them off, and the "on" option turns them on (if the
      device supports it).
      
      Turning ECRC on or off can be a data integrity versus performance
      tradeoff.  In theory, turning it on will catch more data errors, turning
      it off means possibly better performance since CRC does not need to be
      calculated by the PCIe hardware and packet sizes are reduced.
      Signed-off-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      43c16408