DRM's DP helpers take care of dealing with the error code for us. In
order not to step on each other's toes we'll need to be able to simply
read auch channel replies without further logic based on return values.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Access to GPIO needs to be serialized. Aux transactions are already
serialized in DRM but we also need to serialize access to the GPIO pin
for purposes of DP dongle detection.

Call is_dp_sink_present through DM so we can lock correctly. This
follows the same pattern used for DPCD transactions.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHugo Hu <hugo.hu@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

 function description
 get/ set DP configuration: lane_count, link_rate, spread_spectrum

  valid lane count value: 1, 2, 4
  valid link rate value:
  06h = 1.62Gbps per lane
  0Ah = 2.7Gbps per lane
  0Ch = 3.24Gbps per lane
  14h = 5.4Gbps per lane
  1Eh = 8.1Gbps per lane

  debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings

  --- to get dp configuration

  xxd -l 300 phy_settings

  It will list current, verified, reported, preferred dp configuration.
  current -- for current video mode
  verified --- maximum configuration which pass link training
  reported --- DP rx report caps (DPCD register offset 0, 1 2)
  preferred --- user force settings

  --- set (or force) dp configuration

  echo <lane_count>  <link_rate>

  for example, to force to  2 lane, 2.7GHz,
  echo 4 0xa > link_settings

  spread_spectrum could not be changed dynamically.

  in case invalid lane count, link rate are force, no hw programming will be
  done. please check link settings after force operation to see if HW get
  programming.

  xxd -l 300 link_settings

  check current and preferred settings.
Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NHersen Wu <hersenxs.wu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

in case we have very few pins in the table, check fails and we can't boot
Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

add generic indirect register access following our register access pattern

this will make it easier to review code and programming sequence,
with all the complexity hidden in macro
Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
we were using  6 instances based on i2caux_dce110.c

[HOW]
pass in how many instances to ctor
Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

expose dc function to be called by linux dm
Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DCN allows cursor multiplier when blending FP16 surface.
Signed-off-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Megachip dockings accesses ddc line through display driver when
installing FW. Previously, we would fail every transaction because
link attached to mst branch did not have their ddc transaction type
set.

[How]
Set ddc transaction type when mst branch is connected.
Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Separate HUBP surface size and rotation/mirror programming so that
HUBP revision without mirror/rotation do not access those register
fields.
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit cc195141.

This commit was problematic on other OSes. The real solution is to
leave all the error checking to DRM and don't do it in DC, which is
addressed by "Return aux replies directly to DRM" later in this patchset.

v2: Add reason for revert.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit 8a61bc08.

Need to revert "make dm_dp_aux_transfer return payload bytes instead of
size", which this commit is based on. That commit was problematic on
other OSes. The real solution is to leave all the error checking to DRM
and don't do it in DC, which is addressed by "Return aux replies
directly to DRM" later in this patchset.

v2: Add reason for revert.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This shouldn't happen, but if it does, we'll get a backtrace of the
caller, and update the pin_size values as needed.

v2:
* Check bo->pin_count instead of placement flags (Christian König)
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Concurrent execution of the non-atomic arithmetic could result in
completely bogus values.

v2:
* Rebased on v2 of the previous patch

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106872Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

v2:
* Also change amdgpu_vram_mgr_bo_invisible_size to
  amdgpu_vram_mgr_bo_visible_size, allowing further simplification
  (Christian König)

Cc: stable@vger.kernel.org
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

replace run queue by a list of run queues and remove the
sched arg as that is part of run queue itself
Signed-off-by: NNayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Acked-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch is in preparation for a better load balancing in
scheduler. It allows us to associate entities with the
run queues instead of binding them to a scheduler.
Signed-off-by: NNayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Acked-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We are initializing the entity before the scheduler is actually
initialized.

This can lead to all kind of problem, but especially NULL pointer deref
because of Nayan's scheduler work.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Stop using 'magic numbers' when registering interrupt sources.

v2: Switch to kernel style comments.

v3:
Rebase.
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: Rebase
v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts.
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Stop using 'magic numbers' when registering interrupt sources.

v2:
Clean redundant comments.
Switch to kernel style comments.

v3:
Add CP_ECC_ERROR define
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Convert the clocks into right Mhz unit. Otherwise, it will miss
the equal situation.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Gfxoff feature for vega12 is workable. So, there is no need to
mask it any more.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Export apis for enabling/disabling SMU gfxoff support.

v2: fit the latest gfxoff support framework
v3: add feature_mask control
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
change will help to enable gfxoff feature more frequently.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SMU owns this register so the driver should not set it
to avoid breaking gfxoff.

v2: update description
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The save restore list initialization does not have to be pg guarded.
And for some asic(e.g. Vega12), it does not have cntl/gpm/srm lists.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

CSIB init has no relation with rlc version and pg status. It should be
needed regardless of them.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

v2: fit amdgpu_bo_pin change(take one less argument)
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1209:17-18: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Fixes: ea870e44 ("drm/amd/pp: Export notify_smu_enable_pwe to display")
CC: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes: 22cc6c5e (drm/amdgpu: Add runtime VCN PG support)
Signed-off-by: NLeo Liu <leo.liu@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>