Allows you to force the selected performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows you to look at the current DPM state via debugfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for KB/KV asics.  This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed for DPM on CI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

convert from number of lanes to register setting.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Used for vce power management.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for dpm on CI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed for DPM on CI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Uses a different table format if the board supports EVV.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This added support for the on-chip thermal sensors on
CIK asics.

v2: fix register offset.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No support for reading temperature back yet.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Used for uvd power management.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Internally we switched to using a separate header for
atombios pplib definitions.  Switch over the open source
driver.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed for DPM on KB/KV.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

and remove duplicate si_rlc functions.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This will eventually be shared with newer asics to
reduce code duplication.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Restructure rlc setup to handle clock and power
gating.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enables PCIE ASPM (Active State Power Management) on
CIK asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for DPM on CIK.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Calculate the low and high watermarks based on the low and high
clocks for the current power state.  The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Newer asics don't have specific UVD states.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Newer asics have a lot of vram so it's less of an
issue to waste a little more space for the gart
page table.  This gives us some additional gart space
before having to migrate to non-gart system ram
for games, etc. where we use up most of vram.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>