1. 08 4月, 2017 26 次提交
  2. 29 3月, 2017 1 次提交
  3. 20 3月, 2017 1 次提交
  4. 08 3月, 2017 1 次提交
  5. 01 3月, 2017 2 次提交
  6. 25 2月, 2017 1 次提交
  7. 17 2月, 2017 1 次提交
  8. 15 2月, 2017 1 次提交
  9. 08 2月, 2017 2 次提交
  10. 07 2月, 2017 4 次提交
    • D
      drm/msm: return -EFAULT if copy_from_user() fails · 21c42da1
      Dan Carpenter 提交于
      copy_from_user_inatomic() is actually a local function that returns
      -EFAULT or positive values on error.  Otherwise copy_from_user() returns
      the number of bytes remaining to be copied.  We want to return -EFAULT
      here.
      
      I removed an unlikely() because we just did a copy_from_user()
      so I don't think it can possibly make a difference.
      Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      21c42da1
    • A
      drm/msm/dsi: Add PHY/PLL for 8x96 · f079f6d9
      Archit Taneja 提交于
      Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL
      found on 8x96.
      
      These are picked up from the downstream driver. The PHY part is similar
      to the other DSI PHYs. The PLL driver requires some trickery so that
      one DSI PLL can drive both the DSIs (i.e, dual DSI mode).
      
      In the case of dual DSI mode. One DSI instance becomes the clock master,
      and other the clock slave. The master PLL's output (Byte and Pixel clock)
      is fed to both the DSI hosts/PHYs.
      
      When the DSIs are configured in dual DSI mode, the PHY driver communicates
      to the PLL driver using msm_dsi_pll_set_usecase() which instance is the
      master and which one is the slave. When setting rate, the master PLL also
      configures some of the slave PLL/PHY registers which need to be identical
      to the master's for correct dual DSI behaviour.
      
      There are 2 PLL post dividers that should have ideally been modelled as
      generic clk_divider clocks, but require some customization for dual DSI.
      In particular, when the master PLL's post-diviers are set, the slave PLL's
      post-dividers need to be set too. The clk_ops for these use clk_divider's
      helper ops and flags internally to prevent redundant code.
      
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: NArchit Taneja <architt@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      f079f6d9
    • H
      drm/msm/dsi: Add new method to calculate 14nm PHY timings · a4df68fa
      Hai Li 提交于
      The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different
      set of calculations for computing D-PHY timing params. Create a
      timing_calc_v2 func for the newer v2 PHYs.
      Signed-off-by: NHai Li <hali@codeaurora.org>
      Signed-off-by: NArchit Taneja <architt@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      a4df68fa
    • H
      drm/msm/dsi: Move PHY operations out of host · b62aa70a
      Hai Li 提交于
      Since DSI PHY has been a separate platform device, it should not
      depend on the resources in host to be functional. This change is
      to trigger PHY operations in manager, instead of host, so that
      host and PHY can be completely separated.
      Signed-off-by: NHai Li <hali@codeaurora.org>
      Signed-off-by: NArchit Taneja <architt@codeaurora.org>
      Signed-off-by: NRob Clark <robdclark@gmail.com>
      b62aa70a