1. 19 1月, 2017 1 次提交
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  4. 30 12月, 2016 1 次提交
    • S
      arm64: dts: vexpress: Support GICC_DIR operations · 1dff32d7
      Sudeep Holla 提交于
      The GICv2 CPU interface registers span across 8K, not 4K as indicated in
      the DT.  Only the GICC_DIR register is located after the initial 4K
      boundary, leaving a functional system but without support for separately
      EOI'ing and deactivating interrupts.
      
      After this change the system supports split priority drop and interrupt
      deactivation. This patch is based on similar one from Christoffer Dall:
      commit 368400e2 ("ARM: dts: vexpress: Support GICC_DIR operations")
      Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
      1dff32d7
  5. 29 12月, 2016 1 次提交
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  15. 21 11月, 2016 8 次提交