- 09 1月, 2015 2 次提交
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由 Gregory CLEMENT 提交于
This SoC belongs to the Armada 38x family. The main difference with the Armada 385 is that the 388 can handle two more SATA ports. Currently the consequence is the use of a different compatible string for the pinctrl node, in order to be able to use the pins associated to this 2 new SATA ports. The second SATA controller has also been moved from the armada38x.dtsi as it it specific to the Armada388 version. In the same time the Armada385 DB and Armada 385 RD board have been renamed in the 388 one and now include the armada-388.dtsi file. AS both of them have 4 SATA ports the SoC used on them were wrongly described. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
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由 Maxime Ripard 提交于
Some nodes in the DTs have a reg property but no unit name in their node name. This contradicts the way the ePAPR defines the node names. Fix this. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
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- 22 11月, 2014 2 次提交
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由 Marcin Wojtas 提交于
For proper operation of Armada 38x SDHCI controller proper 'clocks' property is sufficient. Therefore it is not useful to keep an additional 'clock-frequency' property in SDHCI controller node of board-level Device Tree file for Armada 385 DB. This commit gets rid of useless 'clock-frequency' property. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NAndrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415980652-7429-4-git-send-email-mw@semihalf.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Marcin Wojtas 提交于
The Marvell Armada 38x SoC's SDHCI interface is capable of using 1.8v voltage, needed for driving "UHS-I" SD cards at their full speed. It is not, however, possible on the DB board. Due to physical connectivity connector supply is tied to 3v and any attempt of changing voltage in order to operate in the fastest UHS modes fails. This patch enables equivalent SDHCI quirk in order to adjust controller operation to system capabilities. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NAndrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415980652-7429-3-git-send-email-mw@semihalf.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 24 6月, 2014 1 次提交
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由 Gregory CLEMENT 提交于
Wildcards in compatible strings should be avoid. "marvell,armada38x" was recently introduced but was not yet used. The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs and more PCIe slots). So this patch replaces the use of "marvell,armada38x" by the "marvell,armada380" string. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1403533011-21339-1-git-send-email-gregory.clement@free-electrons.comAcked-by: NAndrew Lunn <andrew@lunn.ch> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 17 6月, 2014 1 次提交
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由 Ezequiel Garcia 提交于
The factory bootloader on A385-DB boards expect the ECC strength to be 4 bits over 512 bytes. Hence, we need to specify this in the devicetree, to prevent the kernel from assuming any different ECC scheme. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1400941030-2123-3-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 16 5月, 2014 2 次提交
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由 Gregory CLEMENT 提交于
The Marvell Armada 38x SoCs contains one EHCI controller. This commit adds the Device Tree description of this interface at the SoC level, and also enables the USB2 port on the Armada 385 DB platform. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1400149062-32661-16-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
The Marvell Armada 38x SoCs contains two xHCI controllers. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables the two USB3 ports on the Armada 385 DB platform and one USB3 port on the Armada 385 RD platform. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1400149062-32661-15-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 26 4月, 2014 3 次提交
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由 Thomas Petazzoni 提交于
Now that the Armada 370/375/38x/XP SoC-level Device Tree files have the proper "clocks" property in their UART controllers node, it is no longer useful to have the clock-frequency property defined in the board-level Device Tree files. Therefore, this commit gets rid of all the useless 'clock-frequency' properties. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397806908-7550-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The Marvell Armada 38x processors contain two AHCI compatible interfaces. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables them on the Armada 385 DB platform, which allows access to both interfaces through SATA ports. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397574006-5868-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
In commit "mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller", the sdhci-pxav3 driver has been extended to also be usable on Armada 38x platforms. Therefore, this commit adds the necessary Device Tree informations to declare this SDHCI interface in the Armada 38x SoC, and also in the Armada 385 Development Board. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NAndrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1397486478-16991-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 14 3月, 2014 1 次提交
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由 Ezequiel Garcia 提交于
The Armada 385-DB board has a NAND flash, so enable it in the devicetree and add the partitions as prepared in the factory images. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-6-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 07 3月, 2014 1 次提交
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由 Thomas Petazzoni 提交于
On Armada 385 DB, while the "rgmii" PHY connection mode works fine with the generic PHY driver, it fails to work when the Marvell PHY driver is enabled in the kernel configuration, due to a finer handling of the PHY configuration. This is due to the fact that the phy connection mode should instead be "rgmii-id", i.e with the TX/RX delay mechanisms enabled. This fixes the network operation on Armada 385 DB with CONFIG_MARVELL_PHY=y. Without this patch and this option enabled, one would only get messages such as: mvneta f1070000.ethernet eth1: bad rx status 0cc10000 (crc error), size=70 Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 18 2月, 2014 1 次提交
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由 Thomas Petazzoni 提交于
The Armada 385 DB board is the development board from Marvell for the Armada 385 SoC. This commit adds a Device Tree description for this board, which enables the following features: * Network interfaces * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash * PCIe interfaces Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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