1. 05 1月, 2015 1 次提交
    • A
      ARM: imx: correct the hardware clock gate setting for shared nodes · 3d27bc5c
      Anson Huang 提交于
      For those clk gates which hold share count, since its is_enabled
      callback is only checking the share count rather than reading
      the hardware register setting, in the late phase of kernel bootup,
      the clk_disable_unused action will NOT handle the scenario of
      share_count is 0 but the hardware setting is enabled, actually,
      U-Boot normally enables all clk gates, then those shared clk gates
      will be always enabled until they are used by some modules.
      
      So the problem would be: when kernel boot up, the usecount cat
      from clk tree is 0, but the clk gates actually is enabled in
      hardware register, it will confuse user and bring unnecessary power
      consumption.
      
      This patch adds .disable_unused callback and using hardware register
      check for .is_enabled callback of shared nodes to handle such scenario
      in late phase of kernel boot up, then the hardware status will match the
      clk tree info.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      3d27bc5c
  2. 23 9月, 2014 1 次提交
    • S
      ARM: imx: fix .is_enabled() of shared gate clock · 9e1ac462
      Shawn Guo 提交于
      Commit 63288b72 ("ARM: imx: fix shared gate clock") attempted to fix
      an issue with particular enable/disable sequence from two shared gate
      clocks.  But unfortunately, while it partially fixed the issue, it also
      did something wrong in .is_enabled() function hook.  In case of shared
      gate, the function shouldn't really query the hardware state via
      share_count, because the function is trying to query the enabling state
      of the clock in question, not the hardware state which is shared by
      multiple clocks.
      
      Fix the issue by returning the enable_count of the clock itself which is
      maintained by clock core, in case it's a clock sharing hardware gate
      with others.  As the result, the initialization of share_count per
      hardware state is not needed now.  So remove it.
      Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
      Fixes: 63288b72 ("ARM: imx: fix shared gate clock")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      9e1ac462
  3. 08 7月, 2014 1 次提交
    • S
      ARM: imx: fix shared gate clock · 63288b72
      Shawn Guo 提交于
      Let's say clock A and B are two gate clocks that share the same register
      bit in hardware.  Therefore they are registered as shared gate clocks
      with imx_clk_gate2_shared().
      
      In a scenario that only clock A is enabled by clk_enable(A) while B is
      not used, the shared gate will be unexpectedly disabled in hardware.
      It happens because clk_enable(A) increments the share_count from 0 to 1,
      while clock B is unused to clock core, and therefore the core function
      will just disable B by calling clk->ops->disable() directly.  The
      consequence of that call is share_count is decremented to 0 and the gate
      is disabled in hardware, even though clock A is still in use.
      
      The patch fixes the issue by initializing the share_count per hardware
      state and returns enable state per share_count from .is_enabled() hook,
      in case it's a shared gate.
      
      While at it, add a check in clk_gate2_disable() to ensure it's never
      called with a zero share_count.
      Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
      Fixes: f9f28cdf ("ARM: imx: add shared gate clock support")
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      63288b72
  4. 12 5月, 2014 3 次提交
    • S
      ARM: imx: add shared gate clock support · f9f28cdf
      Shawn Guo 提交于
      It's quite common on i.MX that one gate bit controls the gating of
      multiple clocks, i.e. this is a shared gate.  The patch adds the
      function imx_clk_gate2_shared() for such case.  The clocks controlled
      by the same gate bits should call this function with a pointer to a
      single share count variable, so that the gate bits will only be
      operated on the first enabling and the last disabling of these shared
      gate clocks.
      
      Thanks to Gerhard Sittig <gsi@denx.de> for this idea.
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      f9f28cdf
    • S
      ARM: imx: lock is always valid for clk_gate2 · 94b5c028
      Shawn Guo 提交于
      The imx specific clk_gate2 always has a valid lock with the clock.  So
      the validation on gate->lock is not really needed.  Remove it.
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      94b5c028
    • S
      ARM: imx: define struct clk_gate2 on our own · 54ee1471
      Shawn Guo 提交于
      The imx clk-gate2 driver implements an i.MX specific gate clock, which
      has two bits controlling the gate states.  While this is a completely
      separate gate driver from the common clk-gate one, it reuses the common
      clk_gate structure.  Such reusing makes the extending of clk_gate2
      clumsy.  Let's define struct clk_gate2 on our own to make the driver
      independent of the common clk-gate one, and ease the clk_gate2 extending
      at a later time.
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      54ee1471
  5. 31 12月, 2013 1 次提交
  6. 01 4月, 2013 1 次提交
  7. 16 11月, 2012 1 次提交
  8. 02 5月, 2012 2 次提交
    • S
      ARM i.MX: Add common clock support for 2bit gate · b75c0151
      Sascha Hauer 提交于
      This gate consists of two bits:
      
      0b00: clk disabled
      0b01: clk enabled in run mode and disabled in sleep mode
      0b11: clk enabled
      
      Currently only disabled and enabled are supported. As it's unlikely
      that we find something like this in another SoC create a i.MX specific
      clk helper for this.
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      b75c0151
    • S
      clk: Use a separate struct for holding init data. · 0197b3ea
      Saravana Kannan 提交于
      Create a struct clk_init_data to hold all data that needs to be passed from
      the platfrom specific driver to the common clock framework during clock
      registration. Add a pointer to this struct inside clk_hw.
      
      This has several advantages:
      * Completely hides struct clk from many clock platform drivers and static
        clock initialization code that don't care for static initialization of
        the struct clks.
      * For platforms that want to do complete static initialization, it removed
        the need to directly mess with the struct clk's fields while still
        allowing to statically allocate struct clk. This keeps the code more
        future proof even if they include clk-private.h.
      * Simplifies the generic clk_register() function and allows adding optional
        fields in the future without modifying the function signature.
      * Simplifies the static initialization of clocks on all platforms by
        removing the need for forward delcarations or convoluted macros.
      Signed-off-by: NSaravana Kannan <skannan@codeaurora.org>
      [mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Arnd Bergman <arnd.bergmann@linaro.org>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Shawn Guo <shawn.guo@freescale.com>
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Jamie Iles <jamie@jamieiles.com>
      Cc: Richard Zhao <richard.zhao@linaro.org>
      Cc: Saravana Kannan <skannan@codeaurora.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Linus Walleij <linus.walleij@stericsson.com>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Cc: Amit Kucheria <amit.kucheria@linaro.org>
      Cc: Deepak Saxena <dsaxena@linaro.org>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      0197b3ea
  9. 25 4月, 2012 4 次提交
  10. 17 3月, 2012 1 次提交
    • M
      clk: basic clock hardware types · 9d9f78ed
      Mike Turquette 提交于
      Many platforms support simple gateable clocks, fixed-rate clocks,
      adjustable divider clocks and multi-parent multiplexer clocks.
      
      This patch introduces basic clock types for the above-mentioned hardware
      which share some common characteristics.
      
      Based on original work by Jeremy Kerr and contribution by Jamie Iles.
      Dividers and multiplexor clocks originally contributed by Richard Zhao &
      Sascha Hauer.
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      Signed-off-by: NMike Turquette <mturquette@ti.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Tested-by: NAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Arnd Bergman <arnd.bergmann@linaro.org>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Shawn Guo <shawn.guo@freescale.com>
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Jamie Iles <jamie@jamieiles.com>
      Cc: Richard Zhao <richard.zhao@linaro.org>
      Cc: Saravana Kannan <skannan@codeaurora.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Linus Walleij <linus.walleij@stericsson.com>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Cc: Amit Kucheria <amit.kucheria@linaro.org>
      Cc: Deepak Saxena <dsaxena@linaro.org>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      9d9f78ed