All known hardware being able to switch voltages has the same POCCTRL
register. So, factor out the common code to the core and keep only
the pin-to-bit mapping SoC specific. Convert the only user, r8a7790.
In case POCCTRL should ever get more complex (more voltages to select?),
we should probably switch over to a describing array like drive strength
does currently.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Implement the {get,set}_io_voltage operations and set the related
capability flag for the associated pins.
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This macro describes a pinmux configuration that needs configuration in
both a Peripheral Function Select Register (IPSR) and in a
GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the
macro name for clarity.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

Add pins, groups, and a function for SCIF_CLK, which is the external
clock source for the Baud Rate Generator for External Clock (BRG) on
(H)SCIF.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Many SoC needs each PORT_GP_x() macros, but we can share/reuse
same one.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This header file will be removed soon.

Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl
drivers only, to sh_pfc.h, and drop the #include.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but
also various other pinmux-related data (functions and marks).
Every single driver already calls its local array pinmux_data[].
Hence rename the sh_pfc_soc_info member to "pinmux_data".
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

R8A7790/1 PFC  drivers use almost identical  'union vin_data' and completely
identical VIN_DATA_PIN_GROUP() macro; we thus can  move them into the shared
header file...
Suggested-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.

Current PFC driver is very difficult to read, because macro names are
using different length.

	PINMUX_IPSR_NOGP(ispr, ...)
	PINMUX_IPSR_DATA(ipsr, ...)
	PINMUX_IPSR_NOGM(ispr, ...)
	PINMUX_IPSR_NOFN(ipsr, ...)
	PINMUX_IPSR_MSEL(ipsr, ...)
	PINMUX_IPSR_MODSEL_DATA(ipsr, ...)

It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()

	PINMUX_IPSR_NOGP(ispr, ...)
	PINMUX_IPSR_DATA(ipsr, ...)
	PINMUX_IPSR_NOGM(ispr, ...)
	PINMUX_IPSR_NOFN(ipsr, ...)
	PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

GPIO banks 1 and 2 are missing pins 30 and 31. Remove them.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add EtherAVB pin groups to R8A7790 PFC driver.

Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add MLB+ 3-pin mode pin group to R8A7790 PFC driver.

Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The extra entry in the table makes SCIFA0_B, and all
peripherals after it, fail.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NWolfram Sang <wsa@sang-engineering.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the muxing for the last missing i2c rcar core. Fix the sorting for
SH_PFC_PIN_NAMED while we are here.
Signed-off-by: NWolfram Sang <wsa@sang-engineering.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Create a new group for the USB0 OVC/VBUS pin by itself. This
allows us to monitor PWEN as GPIO on the Lager board.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/).
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The arrays are never modified, declare them as const.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There are VIN2 and VIN3 channels available on the R8A7790 SoC.
VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit.
Add both here, covering all possible data pin configurations.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

Both VIN0 and VIN1 channels support identical input interfaces.
Add missing VIN1 pins here and organize them in the same pin
groups as VIN0.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This reorganizes and renames VIN0 data pin groups to cover
all possible configurations. There's total of eight data
pin groups, one per each configuration. Most of the groups
share the same pin/mux array. Only the 18-bit configuration
needs a separate pin/mux array since in combines interleaved
data pins.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This groups VIN0 HSYNC and VSYNC pins together
since one cannot be used without another.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This drops superfluous "signal" word from the pin group names
and renames data_enable group to clkenb as in the h/w manual.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

There are four I2C interfaces on r8a7790, each of them can be connected to
one of the two respective I2C controllers, e.g. interface #0 can be
configured to work with I2C0 or with IIC0. Additionally some of those
interfaces can also use one of several pin sets. Interface #3 is special,
because it can be used in automatic mode for DVFS. It only has one set
of pins available and those pins cannot be used for anything else, they
also lack the GPIO function.

This patch uses the sh-pfc ability to configure pins, not associated with
GPIOs and adds support for I2C3 to the r8a7790 PFC set up.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Adds pinmux for i2c bus 1 and 2. (Pins for 0 and 3 are not multiplexed.)
Signed-off-by: NUlrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Name the DU clock input 1 consistently with clock inputs 0 and 2.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NShinobu Uehara <shinobu.uehara.xc@renesas.com>
Signed-off-by: NRyo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NShinobu Uehara <shinobu.uehara.xc@renesas.com>
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NKunihito Higashiyama <kunihito.higashiyama.ur@renesas.com>
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Navigating through the source code is hard enough without having to
manually search for groups and functions.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Fix erroneous entries in the pinmux configuration tables that affect
HSCIF, I2C, LBSC, SCIF, SSI and VIN operation.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Update the pinmux configuration tables to support the SCIF2 pins
(TX2/TX2_B, RX2/RX2_B, SCK2).
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>