1. 06 2月, 2007 12 次提交
  2. 04 2月, 2007 2 次提交
  3. 05 1月, 2007 1 次提交
    • J
      ACPI: Altix: ACPI _PRT support · 3948ec94
      John Keller 提交于
      Provide ACPI _PRT support for SN Altix systems.
      
      The SN Altix platform does not conform to the
      IOSAPIC IRQ routing model, so a new acpi_irq_model
      (ACPI_IRQ_MODEL_PLATFORM) has been defined. The SN
      platform specific code sets acpi_irq_model to
      this new value, and keys off of it in acpi_register_gsi()
      to avoid the iosapic code path.
      Signed-off-by: NJohn Keller <jpk@sgi.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      3948ec94
  4. 23 12月, 2006 1 次提交
    • I
      [PATCH] sched: fix bad missed wakeups in the i386, x86_64, ia64, ACPI and APM idle code · 0888f06a
      Ingo Molnar 提交于
      Fernando Lopez-Lezcano reported frequent scheduling latencies and audio
      xruns starting at the 2.6.18-rt kernel, and those problems persisted all
      until current -rt kernels. The latencies were serious and unjustified by
      system load, often in the milliseconds range.
      
      After a patient and heroic multi-month effort of Fernando, where he
      tested dozens of kernels, tried various configs, boot options,
      test-patches of mine and provided latency traces of those incidents, the
      following 'smoking gun' trace was captured by him:
      
                       _------=> CPU#
                      / _-----=> irqs-off
                     | / _----=> need-resched
                     || / _---=> hardirq/softirq
                     ||| / _--=> preempt-depth
                     |||| /
                     |||||     delay
         cmd     pid ||||| time  |   caller
            \   /    |||||   \   |   /
        IRQ_19-1479  1D..1    0us : __trace_start_sched_wakeup (try_to_wake_up)
        IRQ_19-1479  1D..1    0us : __trace_start_sched_wakeup <<...>-5856> (37 0)
        IRQ_19-1479  1D..1    0us : __trace_start_sched_wakeup (c01262ba 0 0)
        IRQ_19-1479  1D..1    0us : resched_task (try_to_wake_up)
        IRQ_19-1479  1D..1    0us : __spin_unlock_irqrestore (try_to_wake_up)
        ...
        <idle>-0     1...1   11us!: default_idle (cpu_idle)
        ...
        <idle>-0     0Dn.1  602us : smp_apic_timer_interrupt (c0103baf 1 0)
        ...
         <...>-5856  0D..2  618us : __switch_to (__schedule)
         <...>-5856  0D..2  618us : __schedule <<idle>-0> (20 162)
         <...>-5856  0D..2  619us : __spin_unlock_irq (__schedule)
         <...>-5856  0...1  619us : trace_stop_sched_switched (__schedule)
         <...>-5856  0D..1  619us : trace_stop_sched_switched <<...>-5856> (37 0)
      
      what is visible in this trace is that CPU#1 ran try_to_wake_up() for
      PID:5856, it placed PID:5856 on CPU#0's runqueue and ran resched_task()
      for CPU#0. But it decided to not send an IPI that no CPU - due to
      TS_POLLING. But CPU#0 never woke up after its NEED_RESCHED bit was set,
      and only rescheduled to PID:5856 upon the next lapic timer IRQ. The
      result was a 600+ usecs latency and a missed wakeup!
      
      the bug turned out to be an idle-wakeup bug introduced into the mainline
      kernel this summer via an optimization in the x86_64 tree:
      
          commit 495ab9c0
          Author: Andi Kleen <ak@suse.de>
          Date:   Mon Jun 26 13:59:11 2006 +0200
      
          [PATCH] i386/x86-64/ia64: Move polling flag into thread_info_status
      
          During some profiling I noticed that default_idle causes a lot of
          memory traffic. I think that is caused by the atomic operations
          to clear/set the polling flag in thread_info. There is actually
          no reason to make this atomic - only the idle thread does it
          to itself, other CPUs only read it. So I moved it into ti->status.
      
      the problem is this type of change:
      
              if (!hlt_counter && boot_cpu_data.hlt_works_ok) {
      -               clear_thread_flag(TIF_POLLING_NRFLAG);
      +               current_thread_info()->status &= ~TS_POLLING;
                      smp_mb__after_clear_bit();
                      while (!need_resched()) {
                              local_irq_disable();
      
      this changes clear_thread_flag() to an explicit clearing of TS_POLLING.
      clear_thread_flag() is defined as:
      
              clear_bit(flag, &ti->flags);
      
      and clear_bit() is a LOCK-ed atomic instruction on all x86 platforms:
      
        static inline void clear_bit(int nr, volatile unsigned long * addr)
        {
                __asm__ __volatile__( LOCK_PREFIX
                        "btrl %1,%0"
      
      hence smp_mb__after_clear_bit() is defined as a simple compile barrier:
      
        #define smp_mb__after_clear_bit()       barrier()
      
      but the explicit TS_POLLING clearing introduced by the patch:
      
      +               current_thread_info()->status &= ~TS_POLLING;
      
      is not an atomic op! So the clearing of the TS_POLLING bit is freely
      reorderable with the reading of the NEED_RESCHED bit - and both now
      reside in different memory addresses.
      
      CPU idle wakeup very much depends on ordered memory ops, the clearing of
      the TS_POLLING flag must always be done before we test need_resched()
      and hit the idle instruction(s). [Symmetrically, the wakeup code needs
      to set NEED_RESCHED before it tests the TS_POLLING flag, so memory
      ordering is paramount.]
      
      Fernando's dual-core Athlon64 system has a sufficiently advanced memory
      ordering model so that it triggered this scenario very often.
      
      ( And it also turned out that the reason why these latencies never
        triggered on my testsystems is that i routinely use idle=poll, which
        was the only idle variant not affected by this bug. )
      
      The fix is to change the smp_mb__after_clear_bit() to an smp_mb(), to
      act as an absolute barrier between the TS_POLLING write and the
      NEED_RESCHED read. This affects almost all idling methods (default,
      ACPI, APM), on all 3 x86 architectures: i386, x86_64, ia64.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Tested-by: NFernando Lopez-Lezcano <nando@ccrma.Stanford.EDU>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      0888f06a
  5. 21 12月, 2006 1 次提交
  6. 13 12月, 2006 7 次提交
    • B
      [IA64] kprobe clears qp bits for special instructions · df3e0d1c
      bibo,mao 提交于
      On IA64 there exists some special instructions which
      always need to be executed regradless of qp bits, such
      as com.crel.unc, tbit.trel.unc etc.
      This patch clears qp bits when inserting kprobe trap code
      and disables probepoint on slot 1 for these special
      instructions.
      Signed-off-by: Nbibo,mao <bibo.mao@intel.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      df3e0d1c
    • T
      [IA64] enable trap code on slot 1 · 08ed38b6
      Tony Luck 提交于
      Because slot 1 of one instr bundle crosses border of two consecutive
      8-bytes, kprobe on slot 1 is disabled. This patch enables kprobe on
      slot1, it only replaces higher 8-bytes of the instruction bundle and
      changes the exception code to ignore the low 12 bits of the break
      number (which is across the border in the lower 8-bytes of the bundle).
      
      For those instructions which must execute regardless qp bits,
      kprobe on slot 1 is still disabled.
      Signed-off-by: Nbibo,mao <bibo.mao@intel.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      08ed38b6
    • T
      [IA64] Take defensive stance on ia64_pal_get_brand_info() · 75f6a1de
      Tony Luck 提交于
      Stephane thought he saw a problem here (but was just confused
      by the return value from ia64_pal_get_brand_info()).  But we
      should be more defensive here in case an prototype PAL for
      a future processor doesn't implement this PAL call.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      75f6a1de
    • J
      [IA64] - Reduce overhead of FP exception logging messages · 1cf24bdb
      Jack Steiner 提交于
      Improve the scalability of the fpswa code that rate-limits
      logging of messages.
      
      There are 2 distinctly different problems in this code.
      
      1) If prctl is used to disable logging, last_time is never
         updated. The result is that fpu_swa_count is zeroed out on
         EVERY fp fault. This causes a very very hot cache line.
         The fix reduces the wallclock time of a 1024p FP exception test
         from 28734 sec to 19 sec!!!
      
      2) On VERY large systems, excessive messages are logged because
         multiple cpus can each reset or increment fpu_swa_count at
         about the same time. The result is that hundreds of messages
         are logged each second. The fixes reduces the logging rate
         to ~1 per second.
      Signed-off-by: NJack Steiner <steiner@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      1cf24bdb
    • H
      [IA64] kexec/kdump: tidy up declaration of relocate_new_kernel_t · 53da5763
      Horms 提交于
      * Make NORET_TYPE and ATTRIB_NORET in line with the
        declaration for other architectures
      * Add parameter names
      Signed-Off-By: NSimon Horman <horms@verge.net.au>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      53da5763
    • H
      [IA64] Kexec/Kdump: honour non-zero crashkernel offset. · ad1c3ba7
      Horms 提交于
      There seems to be a value in both allowing the kernel to determine
      the base offset of the crashkernel automatically and allowing
      users's to sepcify it.
      
      The old behaviour on ia64, which is still the current behaviour on
      most architectures is for the user to always specify the address.
      Recently ia64 was changed so that it is always automatically determined.
      
      With this patch the kernel automatically determines the offset if
      the supplied value is 0, otherwise it uses the value provided.
      
      This should probably be backed by a documentation change.
      Signed-Off-By: NSimon Horman <horms@verge.net.au>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      ad1c3ba7
    • H
      [IA64] CONFIG_KEXEC/CONFIG_CRASH_DUMP permutations · 45a98fc6
      Horms 提交于
      Actually, on reflection I think that there is a good case for
      keeping the options separate. I am thinking particularly of people
      who want a very small crashdump kernel and thus don't want to compile
      in kexec.
      
      The patch below should fix things up so that all valid combinations of
      KEXEC, CRASH_DUMP and VMCORE compile cleanly - VMCORE depends on
      CRASH_DUMP which is why I said valid combinations. In a nutshell
      it just untangles unrelated code and switches around a few defines.
      
      Please note that it creats a new file, arch/ia64/kernel/crash_dump.c
      This is in keeping with the i386 implementation.
      Signed-off-by: NSimon Horman <horms@verge.net.au>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      45a98fc6
  7. 09 12月, 2006 1 次提交
  8. 08 12月, 2006 11 次提交
    • Y
      [IA64] replace kmalloc+memset with kzalloc · 52fd9108
      Yan Burman 提交于
      Replace kmalloc+memset with kzalloc
      Signed-off-by: NYan Burman <burman.yan@gmail.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      52fd9108
    • C
      [IA64] resolve name clash by renaming is_available_memory() · 66888a6e
      Christoph Lameter 提交于
      There is a name clash with ia64 arch code in Andrew's tree. Rename
      is_avialable_memory() to is_memory_available() to avoid the clash.
      Signed-off-by: NChristoph Lameter <clameter@sgi.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      66888a6e
    • T
      [IA64] Need export for csum_ipv6_magic · a5f8ee02
      Tony Luck 提交于
      Now we have our own highly optimized assembly code version of
      this routine (Thanks Ken!) we should export it so that it can
      be used.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      a5f8ee02
    • V
      [PATCH] Add support for type argument in PAL_GET_PSTATE · 17e77b1c
      Venkatesh Pallipadi 提交于
      PAL_GET_PSTATE accepts a type argument to return different kinds of
      frequency information.
      Refer: Intel Itanium®Architecture Software Developer's Manual -
      Volume 2: System Architecture, Revision 2.2
      (http://developer.intel.com/design/itanium/manuals/245318.htm)
      
      Add the support for type argument and use Instantaneous frequency
      in the acpi driver.
      
      Also fix a bug, where in return value of PAL_GET_PSTATE was getting compared
      with 'control' bits instead of 'status' bits.
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      17e77b1c
    • R
      [IA64] More Itanium PAL spec updates · 5b4d5681
      Russ Anderson 提交于
      Additional updates to conform with Rev 2.2 of Volume 2 of "Intel
      Itanium Architecture Software Developer's Manual" (January 2006).
      
      Add pal_bus_features_s bits 52 & 53 (page 2:347)
      Add pal_vm_info_2_s field max_purges (page 2:2:451)
      Add PAL_GET_HW_POLICY call (page 2:381)
      Add PAL_SET_HW_POLICY call (page 2:439)
      
      Sample output before:
      ---------------------------------------------------------------------
      cobra:~ # cat /proc/pal/cpu0/vm_info
      Physical Address Space         : 50 bits
      Virtual Address Space          : 61 bits
      Protection Key Registers(PKR)  : 16
      Implemented bits in PKR.key    : 24
      Hash Tag ID                    : 0x2
      Size of RR.rid                 : 24
      Supported memory attributes    : WB, UC, UCE, WC, NaTPage
      ---------------------------------------------------------------------
      
      Sample output after:
      ---------------------------------------------------------------------
      cobra:~ # cat /proc/pal/cpu0/vm_info
      Physical Address Space         : 50 bits
      Virtual Address Space          : 61 bits
      Protection Key Registers(PKR)  : 16
      Implemented bits in PKR.key    : 24
      Hash Tag ID                    : 0x2
      Max Purges                     : 1
      Size of RR.rid                 : 24
      Supported memory attributes    : WB, UC, UCE, WC, NaTPage
      ---------------------------------------------------------------------
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      5b4d5681
    • R
      [IA64] Update processor_info features · 895309ff
      Russ Anderson 提交于
      Add the printing of additional processor features to proc_features.
      
      Based on Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software
      Developer's Manual" (January 2006) fields (pages 2:430-2:432).
      This patch gets the features back in sync with the spec.
      
      Sample output before:
      --------------------------------------------------------------
      cobra:~ # cat /proc/pal/cpu0/processor_info
      XIP,XPSR,XFS implemented                 : On NoCtrl
      XR1-XR3 implemented                      : On NoCtrl
      Disable dynamic predicate prediction     : NotImpl
      Disable processor physical number        : NotImpl
      Disable dynamic data cache prefetch      : NotImpl
      Disable dynamic inst cache prefetch      : NotImpl
      Disable dynamic branch prediction        : NotImpl
      Disable BINIT on processor time-out      : On Ctrl
      Disable dynamic power management (DPM)   : NotImpl
      Disable coherency                        : NotImpl
      Disable cache                            : NotImpl
      Enable CMCI promotion                    : Off Ctrl
      Enable MCA to BINIT promotion            : Off Ctrl
      Enable MCA promotion                     : NotImpl
      Enable BERR promotion                    : NotImpl
      cobra:~ #
      --------------------------------------------------------------
      
      Sample output after:
      --------------------------------------------------------------
      cobra:~ # cat /proc/pal/cpu0/processor_info
      Unimplemented instruction address fault  : NotImpl
      INIT, PMI, and LINT pins                 : NotImpl
      Simple unimplimented instr addresses     : On NoCtrl
      Variable P-state performance             : NotImpl
      Virtual machine features implemeted      : On NoCtrl
      XIP,XPSR,XFS implemented                 : On NoCtrl
      XR1-XR3 implemented                      : On NoCtrl
      Disable dynamic predicate prediction     : NotImpl
      Disable processor physical number        : NotImpl
      Disable dynamic data cache prefetch      : NotImpl
      Disable dynamic inst cache prefetch      : NotImpl
      Disable dynamic branch prediction        : NotImpl
      Disable P-states                         : Off Ctrl
      Enable MCA on Data Poisoning             : Off Ctrl
      Enable vmsw instruction                  : On Ctrl
      Enable extern environmental notification : NotImpl
      Disable BINIT on processor time-out      : On Ctrl
      Disable dynamic power management (DPM)   : NotImpl
      Disable coherency                        : NotImpl
      Disable cache                            : NotImpl
      Enable CMCI promotion                    : Off Ctrl
      Enable MCA to BINIT promotion            : Off Ctrl
      Enable MCA promotion                     : NotImpl
      Enable BERR promotion                    : NotImpl
      cobra:~ #
      --------------------------------------------------------------
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      895309ff
    • M
      [IA64] sparse cleanups · d61b49c1
      Matthew Wilcox 提交于
      0/NULL confusion and some missing UL on constants.
      Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      d61b49c1
    • Z
      [IA64] IA64 Kexec/kdump · a7956113
      Zou Nan hai 提交于
      Changes and updates.
      
      1. Remove fake rendz path and related code according to discuss with Khalid Aziz.
      2. fc.i offset fix in relocate_kernel.S.
      3. iospic shutdown code eoi and mask race fix from Fujitsu.
      4. Warm boot hook in machine_kexec to SN SAL code from Jack Steiner.
      5. Send slave to SAL slave loop patch from Jay Lan.
      6. Kdump on non-recoverable MCA event patch from Jay Lan
      7. Use CTL_UNNUMBERED in kdump_on_init sysctl.
      Signed-off-by: NZou Nan hai <nanhai.zou@intel.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      a7956113
    • I
      [PATCH] hotplug CPU: clean up hotcpu_notifier() use · 02316067
      Ingo Molnar 提交于
      There was lots of #ifdef noise in the kernel due to hotcpu_notifier(fn,
      prio) not correctly marking 'fn' as used in the !HOTPLUG_CPU case, and thus
      generating compiler warnings of unused symbols, hence forcing people to add
      #ifdefs.
      
      the compiler can skip truly unused functions just fine:
      
          text    data     bss     dec     hex filename
       1624412  728710 3674856 6027978  5bfaca vmlinux.before
       1624412  728710 3674856 6027978  5bfaca vmlinux.after
      
      [akpm@osdl.org: topology.c fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      02316067
    • M
      [PATCH] kprobes: enable booster on the preemptible kernel · b4c6c34a
      Masami Hiramatsu 提交于
      When we are unregistering a kprobe-booster, we can't release its
      instruction buffer immediately on the preemptive kernel, because some
      processes might be preempted on the buffer.  The freeze_processes() and
      thaw_processes() functions can clean most of processes up from the buffer.
      There are still some non-frozen threads who have the PF_NOFREEZE flag.  If
      those threads are sleeping (not preempted) at the known place outside the
      buffer, we can ensure safety of freeing.
      
      However, the processing of this check routine takes a long time.  So, this
      patch introduces the garbage collection mechanism of insn_slot.  It also
      introduces the "dirty" flag to free_insn_slot because of efficiency.
      
      The "clean" instruction slots (dirty flag is cleared) are released
      immediately.  But the "dirty" slots which are used by boosted kprobes, are
      marked as garbages.  collect_garbage_slots() will be invoked to release
      "dirty" slots if there are more than INSNS_PER_PAGE garbage slots or if
      there are no unused slots.
      
      Cc: "Keshavamurthy, Anil S" <anil.s.keshavamurthy@intel.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Cc: "bibo,mao" <bibo.mao@intel.com>
      Cc: Prasanna S Panchamukhi <prasanna@in.ibm.com>
      Cc: Yumiko Sugita <yumiko.sugita.yf@hitachi.com>
      Cc: Satoshi Oshima <soshima@redhat.com>
      Cc: Hideo Aoki <haoki@redhat.com>
      Signed-off-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
      Acked-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      b4c6c34a
    • C
      [PATCH] slab: remove SLAB_KERNEL · e94b1766
      Christoph Lameter 提交于
      SLAB_KERNEL is an alias of GFP_KERNEL.
      Signed-off-by: NChristoph Lameter <clameter@sgi.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e94b1766
  9. 07 12月, 2006 1 次提交
  10. 06 12月, 2006 1 次提交
  11. 17 11月, 2006 2 次提交