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  1. 06 9月, 2017 5 次提交
    • C
      MIPS: Add DWARF unwinding to assembly · 866b6a89
      由 Corey Minyard 提交于 
      This will allow kdump dumps to work correclty with MIPS and
future DWARF unwinding of the stack to give accurate tracebacks.
Signed-off-by: NCorey Minyard <cminyard@mvista.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16990/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      866b6a89
    • C
      MIPS: Make SAVE_SOME more standard · 9fef6868
      由 Corey Minyard 提交于 
      Modify the SAVE_SOME macro to look more like a standard
function, doing the arithmetic for the frame on the SP
register instead of copying it from K1, and by saving
the stored EPC from the RA.  This lets the get_frame_info()
function process this function like any other.  It also
remove an instruction or two from the kernel entry,
making it more efficient.

unwind_stack_by_address() has special handling for
the top of the interrupt stack, but without this change
unwinding will still fail if you get an interrupt while
handling an interrupt and try to do a traceback from
the second interrupt.

This change modifies the get_saved_sp macro to
optionally store the fetched value right into sp and store the
old SP value into K0.  Then it's just a matter of subtracting
the frame from SP and storing the old SP from K0.

This required changing the DADDI workaround a bit, since K0
holds the SP, we had to use K1 for AT.  But it eliminated
some of the special handling for the DADDI workaround.

Saving the RA register was moved up to before fetching the
CP0_EPC register, so the CP0_EPC register could be stored
into RA and the saved.  This lets the traceback code know
where RA is actually stored.
Signed-off-by: NCorey Minyard <cminyard@mvista.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16991/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      9fef6868
    • C
      MIPS: Fix issues in backtraces · aee16625
      由 Corey Minyard 提交于 
      I saw two problems when doing backtraces:

The compiler was putting a "fast return" at the top of some
functions, before it set up the frame.  The backtrace code
would stop when it saw a jump instruction, so it would never
get to the stack frame setup and would thus misinterpret it.
To fix this, don't look for jump instructions until the
frame setup has been seen.

The assembly code here is:

ffffffff80b885a0 <serial8250_handle_irq>:
ffffffff80b885a0:       c8a00003        bbit0   a1,0x0,ffffffff80b885b0 <serial8250_handle_irq+0x10>
ffffffff80b885a4:       0000102d        move    v0,zero
ffffffff80b885a8:       03e00008        jr      ra
ffffffff80b885ac:       00000000        nop
ffffffff80b885b0:       67bdffd0        daddiu  sp,sp,-48
ffffffff80b885b4:       ffb00008        sd      s0,8(sp)

The second problem was the compiler was putting the last
instruction of the frame save in the delay slot of the
jump instruction.  If it saved the RA in there, the
backtrace could would miss it and misinterpret the frame.
To fix this, make sure to process the instruction after
the first jump seen.

The assembly code for this is:

ffffffff80806fd0 <plat_irq_dispatch>:
ffffffff80806fd0:       67bdffd0        daddiu  sp,sp,-48
ffffffff80806fd4:       ffb30020        sd      s3,32(sp)
ffffffff80806fd8:       24130018        li      s3,24
ffffffff80806fdc:       ffb20018        sd      s2,24(sp)
ffffffff80806fe0:       3c12811c        lui     s2,0x811c
ffffffff80806fe4:       ffb10010        sd      s1,16(sp)
ffffffff80806fe8:       3c11811c        lui     s1,0x811c
ffffffff80806fec:       ffb00008        sd      s0,8(sp)
ffffffff80806ff0:       3c10811c        lui     s0,0x811c
ffffffff80806ff4:       08201c03        j       ffffffff8080700c <plat_irq_dispa
tch+0x3c>
ffffffff80806ff8:       ffbf0028        sd      ra,40(sp)
Signed-off-by: NCorey Minyard <cminyard@mvista.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16992/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      aee16625
    • M
      MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree · ed326616
      由 Mathieu Malaterre 提交于 
      The jz4740-rtc driver supports both jz4740 & jz4780, setup the compatible
string to jz4780.
Signed-off-by: NMathieu Malaterre <malat@debian.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Paul Cercueil <paul@crapouillou.net>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17237/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ed326616
    • M
      MIPS: Ci20: Enable RTC driver · c76a5ba2
      由 Mathieu Malaterre 提交于 
      Update the Ci20's defconfig to enable the JZ4780's RTC driver.
Signed-off-by: NMathieu Malaterre <malat@debian.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Paul Cercueil <paul@crapouillou.net>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17236/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c76a5ba2
  3. 05 9月, 2017 13 次提交
  5. 04 9月, 2017 11 次提交
  7. 02 9月, 2017 1 次提交
  9. 30 8月, 2017 10 次提交
    • P
      MIPS: GIC: Introduce asm/mips-gic.h with accessor functions · 582e2b4a
      由 Paul Burton 提交于 
      This patch introduces a new header providing accessor functions for the
MIPS Global Interrupt Controller (GIC) mirroring those provided for the
other 2 components of the MIPS Coherent Processing System (CPS) - the
Coherence Manager (CM) & Cluster Power Controller (CPC).

This header makes use of the new standardised CPS accessor macros where
possible, but does require some custom accessors for cases where we have
either a bit or a register per interrupt.

A major advantage of this over the existing
include/linux/irqchip/mips-gic.h definitions is that code performing
accesses can become much simpler, for example this:

  gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
                  GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
                  (unsigned long)trig << GIC_INTR_BIT(intr));

...can become simply:

  change_gic_trig(intr, trig);

The accessors handle 32 vs 64 bit in the same way as for CM & CPC code,
which means that GIC code will also not need to worry about the access
size in most cases. They are also accessible outside of
drivers/irqchip/irq-mips-gic.c which will allow for simplification in
the use of the non-interrupt portions of the GIC (eg. counters) which
currently require the interrupt controller driver to expose helper
functions for access.

This patch doesn't change any existing code over to use the new
accessors yet, since a wholesale change would be invasive & difficult to
review. Instead follow-on patches will convert code piecemeal to use
this new header. The one change to existing code is to rename gic_base
to mips_gic_base & make it global, in order to fit in with the naming
expected by the standardised CPS accessor macros.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17020/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      582e2b4a
    • C
      MIPS: Don't use dma_cache_sync to implement fd_cacheflush · 1dd71588
      由 Christoph Hellwig 提交于 
      The floppy drivers doesn't otherwise use the DMA API, so indirecting
through it just for cache flushing in MIPS-specific code just call
dma_cache_wback_inv directly.
Signed-off-by: NChristoph Hellwig <hch@lst.de>
Cc: iommu@lists.linux-foundation.org
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: David Howells <dhowells@redhat.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: x86@kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-ia64@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-xtensa@linux-xtensa.org
Cc: linux-sh@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17183/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1dd71588
    • P
      MIPS: generic: Bump default NR_CPUS to 16 · c2c03291
      由 Paul Burton 提交于 
      In generic_defconfig set CONFIG_NR_CPUS to 16 rather than 2, which is a
rather too low limit for many modern day MIPS systems.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16949/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c2c03291
    • P
      MIPS: generic: Don't explicitly disable CONFIG_USB_SUPPORT · f8bfffc1
      由 Paul Burton 提交于 
      Leave CONFIG_USB_SUPPORT at its default, allowing board config fragments
to make use of USB drivers without needing to override it & trigger
warnings from merge_config.sh.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16948/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f8bfffc1
    • P
      MIPS: Make CONFIG_MIPS_MT_SMP default y · 5cbf9688
      由 Paul Burton 提交于 
      On systems that support MT ASE multithreading (ie. VPEs) we are very
likely to want to include that support as default. Rather than setting
it in various defconfigs, simply make CONFIG_MIPS_MT_SMP default y such
that systems which select CONFIG_SYS_SUPPORTS_MULTITHREADING get it by
default.

As well as allowing us to remove the selection of CONFIG_MIPS_MT_SMP
from various defconfigs, this also allows the generated generic
defconfigs which derive from generic_defconfig to automatically gain
support for MT ASE SMP when building for a suitable (pre-MIPSr6) ISA.

For malta_kvm_guest_defconfig CONFIG_MIPS_MT_SMP is explicitly disabled
since enabling SMP implicitly disables CONFIG_KVM_GUEST, which depends
on CONFIG_BROKEN_ON_SMP.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16947/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5cbf9688
    • P
      MIPS: Prevent direct use of generic_defconfig · a4c2f797
      由 Paul Burton 提交于 
      Using generic_defconfig directly is unlikely to be what a user actually
wants to do - it doesn't specify any particular ISA revision & it
doesn't enable any board or driver support, resulting in a largely
useless kernel.

Prevent users from using it directly, printing a helpful message to
point them in the right direction if they attempt to.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16946/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a4c2f797
    • P
      MIPS: NI 169445: Only include in 32r2el kernels · 9e111ee7
      由 Paul Burton 提交于 
      The NI 169445 board uses a little endian MIPS32r2 CPU, and therefore
including board support in kernels that are unable to run on such a CPU
is pointless.

Specify requirements in the board config fragment that cause the NI
169445 board support to only be included in generic kernels that target
little endian MIPS32r2 CPUs.

For example, NI 169445 support will be included when configuring using
32r2el_defconfig but not when using 64r6_defconfig.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NNathan Sullivan <nathan.sullivan@ni.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16945/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      9e111ee7
    • P
      MIPS: SEAD-3: Only include in 32 bit kernels by default · c7a1d3d8
      由 Paul Burton 提交于 
      The MIPS SEAD-3 development board has only ever been used with 32 bit
CPUs, so including support for it in 64 bit kernels is wasteful since
those kernels will never run on a SEAD-3.

Specify a requirement in the SEAD-3 board config fragment that ensures
the board support is only included in 32 bit kernels, by checking that
CONFIG_32BIT=y.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16944/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c7a1d3d8
    • P
      MIPS: generic: Allow filtering enabled boards by requirements · 27e0d4b0
      由 Paul Burton 提交于 
      Up until now when configuring a generic kernel all board config
fragments have been merged by default unless boards are explicitly
selected by the user specifying BOARDS=.

In many cases this is sub-optimal, since some boards don't make sense to
include in some kernels. For example the MIPS SEAD-3 development board
has only ever been used with 32 bit CPUs, so including support for the
SEAD-3 in a 64 bit kernel is wasteful.

This patch introduces support for specifying requirements in board
config fragments, using comments formatted like so:

  # require CONFIG_BLA=y

For example the SEAD-3 board could specify that it should only be merged
for 32 bit kernels using a requirement line like the following:

  # require CONFIG_32BIT=y

A new generic-board-config.sh script is introduced to handle selecting
the board config fragments to merge & calling merge_config.sh to merge
them. In order to allow requirements to check Kconfig symbols that are
implicitly selected, rather than explicitly specified by
generic_defconfig or one of the ISA config fragments, an intermediate
.config file is saved & used as a reference when checking requirements.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16943/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      27e0d4b0
    • P
      MIPS: CPS: Detect CPUs in secondary clusters · 1ec9dd80
      由 Paul Burton 提交于 
      As a first step towards supporting multi-cluster systems, detect cores &
VPs in secondary clusters & record their cluster information in the
cpu_data array. The "VP topology" line printed during boot is extended
to display multiple clusters. On a single cluster it shows output like
the following:

  VP topology: {4,4}

This would indicate a system with 2 cores which each contain 4 VPs. We
extend this to cover multiple clusters in a natural way:

  VP topology: {4,4},{2,2}

This would indicate a system with 2 clusters. The first cluster contains
2 cores which each contain 4 VPs. The second cluster contains 2 cores
which each contain 2 VPs.

Actually booting these cores & VPs is left to further patches once other
pieces are in place.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17017/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1ec9dd80