1. 07 12月, 2016 11 次提交
    • S
      net: hns: Fix to conditionally convey RX checksum flag to stack · 862b3d20
      Salil 提交于
      This patch introduces the RX checksum function to check the
      status of the hardware calculated checksum and its error and
      appropriately convey status to the upper stack in skb->ip_summed
      field.
      
      In hardware, we only support checksum for the following
      protocols:
      1) IPv4,
      2) TCP(over IPv4 or IPv6),
      3) UDP(over IPv4 or IPv6),
      4) SCTP(over IPv4 or IPv6)
      but we support many L3(IPv4, IPv6, MPLS, PPPoE etc) and
      L4(TCP, UDP, GRE, SCTP, IGMP, ICMP etc.) protocols.
      
      Hardware limitation:
      Our present hardware RX Descriptor lacks L3/L4 checksum
      "Status & Error" bit (which usually can be used to indicate whether
      checksum was calculated by the hardware and if there was any error
      encountered during checksum calculation).
      
      Software workaround:
      We do get info within the RX descriptor about the kind of
      L3/L4 protocol coming in the packet and the error status. These
      errors might not just be checksum errors but could be related to
      version, length of IPv4, UDP, TCP etc.
      Because there is no-way of knowing if it is a L3/L4 error due
      to bad checksum or any other L3/L4 error, we will not (cannot)
      convey hardware checksum status(CHECKSUM_UNNECESSARY) for such
      cases to upper stack and will not maintain the RX L3/L4 checksum
      counters as well.
      Signed-off-by: NSalil Mehta <salil.mehta@huawei.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      862b3d20
    • I
      net: ethernet: ti: cpsw: fix early budget split · 48e0a83e
      Ivan Khoronzhuk 提交于
      The budget split function requires the phy speed to be known.
      While ndo open a phy speed identification is postponed till the
      moment link is up. Hence, move it to appropriate callback, when link
      is up.
      Reported-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Fixes: 8feb0a19 ("net: ethernet: ti: cpsw: split tx budget according between channels")
      Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      48e0a83e
    • F
      Revert "dctcp: update cwnd on congestion event" · 343dfaa1
      Florian Westphal 提交于
      Neal Cardwell says:
       If I am reading the code correctly, then I would have two concerns:
       1) Has that been tested? That seems like an extremely dramatic
          decrease in cwnd. For example, if the cwnd is 80, and there are 40
          ACKs, and half the ACKs are ECE marked, then my back-of-the-envelope
          calculations seem to suggest that after just 11 ACKs the cwnd would be
          down to a minimal value of 2 [..]
       2) That seems to contradict another passage in the draft [..] where it
          sazs:
             Just as specified in [RFC3168], DCTCP does not react to congestion
             indications more than once for every window of data.
      
      Neal is right.  Fortunately we don't have to complicate this by testing
      vs. current rtt estimate, we can just revert the patch.
      
      Normal stack already handles this for us: receiving ACKs with ECE
      set causes a call to tcp_enter_cwr(), from there on the ssthresh gets
      adjusted and prr will take care of cwnd adjustment.
      
      Fixes: 47805667 ("dctcp: update cwnd on congestion event")
      Cc: Neal Cardwell <ncardwell@google.com>
      Signed-off-by: NFlorian Westphal <fw@strlen.de>
      Acked-by: NNeal Cardwell <ncardwell@google.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      343dfaa1
    • D
      Merge branch 'mv88e6xxx-rework-reset-and-PPU-code' · b1df0f5c
      David S. Miller 提交于
      Vivien Didelot says:
      
      ====================
      net: dsa: mv88e6xxx: rework reset and PPU code
      
      Old Marvell chips (like 88E6060) don't have a PHY Polling Unit (PPU).
      
      Next chips (like 88E6185) have a PPU, which has exclusive access to the
      PHY registers, thus must be disabled before access.
      
      Newer chips (like 88E6352) have an indirect mechanism to access the PHY
      registers whenever, thus loose control over the PPU (always enabled).
      
      Here's a summary:
      
      Model | PPU? | Has PPU ctrl?  | PPU state readable? | PHY access
      ----- | ---- | -------------- | ------------------- | ----------
       6060 | no   | no             | no                  | direct
       6185 | yes  | yes, PPUEn bit | yes, PPUState 2-bit | direct w/ PPU dis.
       6352 | yes  | no             | yes, PPUState 1-bit | indirect
       6390 | yes  | no             | yes, InitState bit  | indirect
      
      Depending on the PPU control, a switch may have to restart the PPU when
      resetting the switch. Once the switch is reset, we must wait for the PPU
      state to be active polling again before accessing the registers.
      
      For that purpose, add new operations to the chips to enable/disable the
      PPU, and execute software reset. With these new ops in place, rework the
      switch reset code and finally get rid of the MV88E6XXX_FLAG_PPU* flags.
      
      Changes in v3:
        - consider 6097 as 6352 (no PPU ops and use mv88e6352_g1_reset).
      
      Changes in v2:
        - wait in ppu/reset ops so that ppu_polling is not needed anymore.
      ====================
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b1df0f5c
    • V
      net: dsa: mv88e6xxx: add PPU operations · a199d8b6
      Vivien Didelot 提交于
      Some Marvell chips can enable/disable the PPU on demand. This is needed
      to access the PHY registers when there is no indirection mechanism.
      
      Add two new ppu_enable and ppu_disable ops to describe this and finally
      get rid of the MV88E6XXX_FLAG_PPU* flags.
      Signed-off-by: NVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a199d8b6
    • V
      net: dsa: mv88e6xxx: add a soft reset operation · 17e708ba
      Vivien Didelot 提交于
      Marvell chips have different way to issue a software reset.
      
      Old chips (such as 88E6060) have a reset bit in an ATU control register.
      
      Newer chips moved this bit in a Global control register. Chips with
      controllable PPU should reset the PPU when resetting the switch.
      
      Add a new reset operation to implement these differences and introduce a
      mv88e6xxx_software_reset() helper to wrap it conveniently.
      Signed-off-by: NVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      17e708ba
    • V
      net: dsa: mv88e6xxx: add helper to hardware reset · 309eca6d
      Vivien Didelot 提交于
      Add an helper to toggle the eventual GPIO connected to the reset pin.
      Signed-off-by: NVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      309eca6d
    • V
      net: dsa: mv88e6xxx: add helper to disable ports · 4ac4b5a6
      Vivien Didelot 提交于
      Before resetting a switch, the ports should be set to the Disabled state
      and the transmit queues should be drained.
      
      Add an helper to explicit that.
      Signed-off-by: NVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4ac4b5a6
    • D
      Merge branch 'Alacritech-SLIC-driver' · 9f9ffdff
      David S. Miller 提交于
      Lino Sanfilippo says:
      
      ====================
      Gigabit ethernet driver for Alacritechs SLIC devices (v4)
      
      this is the forth version of the slicoss gigabit ethernet driver (which is a
      rework of the driver from Alacritech which can currently be found under
      drivers/staging/slicoss). The driver is supposed to support Mojave, Oasis and
      Kalahari cards, for both copper and fiber.
      
      If this code is accepted the staging version can be removed.
      
      The driver has been tested on a SEN2104ET adapter (4 Port PCIe copper).
      
      v4:
      - fix wrong driver name in Kconfig file (reported by Rami Rosen)
      - remove unused variable from driver struct (reported by Rami Rosen)
      - return "err" instead of 0 in slic_load_rcvseq_firmware() (reported by Rami Rosen)
      - Fix typos in constants, comments and error message (reported by Markus Böhme)
      - fix various warnings concerning signedness (reported by Markus Böhme)
      - improve line formatting (reported by Markus Böhme)
      - add comment describing the need for SLIC_MAX_TX_COMPLETIONS (suggested by Florian Fainelli)
      - do not zero out complete rx descriptor (suggested by Florian Fainelli)
      - add missing write barrier (reported by Florian Fainelli)
      - remove unneeded assignment of net_device to skb (reported by Florian Fainelli)
      - use napi_complete_done() instead of napi_complete (suggested by Florian Fainelli)
      - use napi_schedule_irqoff() instead of napi_schedule (suggested by Florian Fainelli)
      - do not map error returned by slic_init() to -ENOMEM
      - do proper dma syncs before and after rx descriptor status is set to 0
      - if after dma sync for CPU rx descriptor is not used return it to HW by means of dma sync for device
      
      v3:
      - dont add defines to pci_ids.h but instead put it into the drivers header file
      (requested by Greg Kroah-Hartman)
      
      v2:
      - remove unusual padding in statistic strings (suggested by Andrew Lunn)
      - for mdio register and bit names use defines from mii.h instead of own ones
        (suggested by Andrew Lunn)
      - remove unused defines
      - ensure PCI flush at two more places
      - use mmiowb before lock to prevent mmio writes leaking out of lock
      - fix some typos in comments
      - add copyright and GPL header
      ====================
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9f9ffdff
    • L
      MAINTAINERS: add entry for slicoss ethernet driver · b9567027
      Lino Sanfilippo 提交于
      Add myself as maintainer for the slicoss ethernet driver.
      Signed-off-by: NLino Sanfilippo <LinoSanfilippo@gmx.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b9567027
    • L
      net: ethernet: slicoss: add slicoss gigabit ethernet driver · 60c140df
      Lino Sanfilippo 提交于
      Add driver for Alacritech gigabit ethernet cards with SLIC (session-layer
      interface control) technology. The driver provides basic support without
      SLIC for the following devices:
      
      - Mojave cards (single port PCI Gigabit) both copper and fiber
      - Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
      - Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
      Signed-off-by: NLino Sanfilippo <LinoSanfilippo@gmx.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      60c140df
  2. 06 12月, 2016 29 次提交