1. 29 2月, 2016 1 次提交
  2. 22 12月, 2015 1 次提交
    • Y
      mmc: sdhci-of-esdhc: add/remove some quirks according to vendor version · 1ef5e49e
      yangbo lu 提交于
      A previous patch had removed esdhc_of_platform_init() by mistake.
      static void esdhc_of_platform_init(struct sdhci_host *host)
      {
      	u32 vvn;
      
      	vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
      	vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
      	if (vvn == VENDOR_V_22)
      		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
      
      	if (vvn > VENDOR_V_22)
      		host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
      }
      
      This patch is used to fix it by add/remove some quirks according to
      verdor version in probe.
      Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
      Fixes: f4932cfd ("mmc: sdhci-of-esdhc: support both BE and LE host controller")
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      1ef5e49e
  3. 26 10月, 2015 4 次提交
  4. 27 8月, 2015 1 次提交
  5. 01 6月, 2015 2 次提交
  6. 23 3月, 2015 1 次提交
  7. 19 1月, 2015 2 次提交
  8. 09 9月, 2014 1 次提交
  9. 23 5月, 2014 1 次提交
  10. 22 5月, 2014 6 次提交
  11. 27 9月, 2013 1 次提交
  12. 26 9月, 2013 1 次提交
  13. 26 8月, 2013 1 次提交
  14. 06 7月, 2013 2 次提交
  15. 27 6月, 2013 1 次提交
  16. 31 5月, 2013 1 次提交
  17. 23 3月, 2013 2 次提交
  18. 07 12月, 2012 2 次提交
  19. 29 11月, 2012 3 次提交
  20. 08 11月, 2012 1 次提交
  21. 05 9月, 2012 1 次提交
  22. 26 3月, 2012 2 次提交
  23. 12 2月, 2012 1 次提交
    • R
      mmc: esdhc: fix errors when booting kernel on Freescale eSDHC version 2.3 · ba8c4dc9
      Roy Zang 提交于
      When eSDHC module is enabled on P5020/P3041/P2041/P1010 with eSDHC
      version 2.3, there is following errors:
      
      mmc0: Timeout waiting for hardware interrupt.
      mmc0: error -110 whilst initialising SD card
      mmc0: Unexpected interrupt 0x02000000.
      mmc0: Timeout waiting for hardware interrupt.
      mmc0: error -110 whilst initialising SD card
      mmc0: Unexpected interrupt 0x02000000.
      
      It is because eSDHC controller has different bit setting for PROCTL
      register at 0x28 comparing SD specification.
      This patch sets DMAS bits correctly for byte operation and does not
      change the default value of other field of PROCTL register.
      
      For other FSL chips, such as MPC8536/P2020, PROCTL[DMAS]
      bits are reserved and even if they are set to wrong bits, it will not
      take effective.
      Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
      Acked-by: NAnton Vorontsov <cbouatmailru@gmail.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      ba8c4dc9
  24. 12 1月, 2012 1 次提交