Add QSPI node support, and this function is disabled by default
This setting could be overwritten in board-level definitions
Signed-off-by: NSZ Lin <sz.lin@moxa.com>
Acked-by: NLi Yang <leoyang.li@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

qoriq clock driver has been updated to parse the clock configuration
information defined in driver itself not in dts.
Since the new implementation and the bindings have been merged,
it is time to update the clock related node and remove redundent clock
configuration information from the dts.
Signed-off-by: NTang Yuantian <andy.tang@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Also add nodes and properties for thermal management support.
Signed-off-by: NJia Hongtao <hongtao.jia@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The DCU IP has distinct clock inputs for register access and the
pixel clocks, at least in some implementations. LS1021a seems to
use the same clock, therefore specify the same clock for "dcu"
and "pix".
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Both DSPI have signals SPIn_PCS[0:5] so in summary 6 chip-selects, not 5.
Fix that.
Signed-off-by: NAlexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add gpio nodes for ls1021a platform dts file. The gpio
IP block of the ls1021a can be supported by the code
drivers/gpio/gpio-mpc8xxx.c.

The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.

The chip-specific compatible "fsl,ls1021a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: NLiu Gang <Gang.Liu@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add SCFG MSI dts node and add msi-parent property to PCIe dts node
that points to the corresponding MSI node.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: NAlexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

LS1021a contains two PCIe controllers. The patch adds their node to
dts file.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add the 1588 timer node for ls1021a platform to
support gianfar ptp driver.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Added sata node to ls1021aqds and ls1021atwr board to support
sata function.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Signed-off-by: NAlison Wang <b18965@freescale.com>
Signed-off-by: NXiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
Signed-off-by: NMeng Yi <b56799@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add "snps,quirk-frame-length-adjustment" property to
USB3 node for erratum A009116. This property provides
value of GFLADJ_30MHZ for post silicon frame length
adjustment.
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This patch adds dma-coherent property for eTSEC nodes, so
coherent DMA operations are supported.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Signed-off-by: NHoria Geantă <horia.geanta@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This patch adds dts nodes for audio on LS1021A.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Freescale DSPI driver has been updated and supports TCF interrupt type now.
In the new driver we choose the interrupt type according the compatible
string of the device node.
This patch update the compatible string of DSPI device node of LS1021A in
order to use the correct interrupt type.
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

On LS1021A SoC, the scfg device is in BE mode.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This add Freescale QorIQ LS1021A SoC device tree support.
The QorIQ LS1021A processor incorporates dual ARM Cortex-A7 cores,
providing virtualization support, advanced security features and the
broadest array of high-speed interconnects and optimized peripheral
features.

The LS1021A SoC shares IPs with i.MX, Vybrid and PowerPC platform.

For the detail information about Freescale QorIQ LS1021A SoC,
please refer to the QorIQ LS1021A Reference Manual.
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: NChenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NChao Fu <b44548@freescale.com>
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NJingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>