ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.

Note that cache flushing on SMP systems now takes place via the
set_pte_at() call (__sync_icache_dcache) and there is no race with other
CPUs executing code from the new PTE before the cache flushing took
place.
Tested-by: NRabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the current cache maintenance operations in
update_mmu_cache(). To avoid this, cache maintenance must be handled in
set_pte_at() (similar to IA-64 and PowerPC).

This patch provides a unified VIPT cache handling mechanism and
implements the __sync_icache_dcache() function for ARMv6 onwards
architectures. It is called from set_pte_at() and replaces the
update_mmu_cache(). The latter is still used on VIVT hardware where a
vm_area_struct is required.
Tested-by: NRabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().
Tested-by: NRabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Commit d73cd428 forced non-lazy cache flushing of highmem pages in
flush_dcache_page(). This isn't needed since __flush_dcache_page()
(called lazily from update_mmu_cache) can handle highmem pages (fixed by
commit 7e5a69e8).
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

If a signal hits us outside of a syscall and another gets delivered
when we are in sigreturn (e.g. because it had been in sa_mask for
the first one and got sent to us while we'd been in the first handler),
we have a chance of returning from the second handler to location one
insn prior to where we ought to return.  If r0 happens to contain -513
(-ERESTARTNOINTR), sigreturn will get confused into doing restart
syscall song and dance.

Incredible joy to debug, since it manifests as random, infrequent and
very hard to reproduce double execution of instructions in userland
code...

The fix is simple - mark it "don't bother with restarts" in wrapper,
i.e. set r8 to 0 in sys_sigreturn and sys_rt_sigreturn wrappers,
suppressing the syscall restart handling on return from these guys.
They can't legitimately return a restart-worthy error anyway.

Testcase:
	#include <unistd.h>
	#include <signal.h>
	#include <stdlib.h>
	#include <sys/time.h>
	#include <errno.h>

	void f(int n)
	{
		__asm__ __volatile__(
			"ldr r0, [%0]\n"
			"b 1f\n"
			"b 2f\n"
			"1:b .\n"
			"2:\n" : : "r"(&n));
	}

	void handler1(int sig) { }
	void handler2(int sig) { raise(1); }
	void handler3(int sig) { exit(0); }

	main()
	{
		struct sigaction s = {.sa_handler = handler2};
		struct itimerval t1 = { .it_value = {1} };
		struct itimerval t2 = { .it_value = {2} };

		signal(1, handler1);

		sigemptyset(&s.sa_mask);
		sigaddset(&s.sa_mask, 1);
		sigaction(SIGALRM, &s, NULL);

		signal(SIGVTALRM, handler3);

		setitimer(ITIMER_REAL, &t1, NULL);
		setitimer(ITIMER_VIRTUAL, &t2, NULL);

		f(-513); /* -ERESTARTNOINTR */

		write(1, "buggered\n", 9);
		return 1;
	}
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Cc: stable@kernel.org
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The sd/mmc data structure is not used if SPI is selected. The configuration
of PIO on the board prevent from using both interfaces at the same time
(board dependent).
Remove the warnings at compilation time adding a preprocessor condition.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add information in dm9000 mac/phy chip initialization:
- irq resource details
- platform data details
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Partially revert e69edc79, which introduced automatic zreladdr
support.  The change in the way the manual definition is defined
seems to be error and conflict prone.  Go back to the original way
we were handling this for the time being, while keeping the automatic
zreladdr facility.

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Without this patch you will not be able to register the first block
because of the second association call on at91_add_device_tc().
Signed-off-by: NFabian Godehardt <fg@emlix.com>
[nicolas.ferre@atmel.com: change tcb1_clk to fake child clock of tcb0_clk]
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

While registering clock allow to set parent clock other
than mck. It is useful for clocks than can be seen as
child clock of a peripheral.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NAndrew Victor <linux@maxim.org.za>

Dave Hylands reports:
| We've observed a problem with dma_alloc_writecombine when the system
| is under heavy load (heavy bus traffic).  We've managed to reduce the
| problem to the following snippet, which is run from a kthread in a
| continuous loop:
|
|   void *virtAddr;
|   dma_addr_t physAddr;
|   unsigned int numBytes = 256;
|
|   for (;;) {
|       virtAddr = dma_alloc_writecombine(NULL,
|             numBytes, &physAddr, GFP_KERNEL);
|       if (virtAddr == NULL) {
|          printk(KERN_ERR "Running out of memory\n");
|          break;
|       }
|
|       /* access DMA memory allocated */
|       tmp = virtAddr;
|       *tmp = 0x77;
|
|       /* free DMA memory */
|       dma_free_writecombine(NULL,
|             numBytes, virtAddr, physAddr);
|
|         ...sleep here...
|     }
|
| By itself, the code will run forever with no issues. However, as we
| increase our bus traffic (typically using DMA) then the *tmp = 0x77
| line will eventually cause a page fault. If we add a small delay (a
| few microseconds) before the *tmp = 0x77, then we don't see a page
| fault, even under heavy load.

A dsb() is required after modifying the PTE entries to ensure that they
will always be visible.  Add this dsb().
Reported-by: NDave Hylands <dhylands@gmail.com>
Tested-by: NDave Hylands <dhylands@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Commit 7cfe2494 ("ARM: AMBA: Add pclk support to AMBA bus
infrastructure") changed AMBA bus to handle the PCLK automatically.
However, in EP93xx clock initialization is arch_initcall which is done
later than AMBA device identification. This causes
amba_get_enable_pclk() to fail resulting device where UARTs are not
functional.

So change ep93xx_clock_init() to be postcore_initcall.
Signed-off-by: NMika Westerberg <mika.westerberg@iki.fi>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This reverts commit 4fa5518c, which causes a compilation regression for
IXP4xx platforms.
Reported-by: NRichard Cochran <richardcochran@gmail.com>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Reported-by: NDan Liang <dan.liang@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The validate_event function in the ARM perf events backend has the
following problems:

1.) Events that are disabled count towards the cost.
2.) Events associated with other PMUs [for example, software events or
    breakpoints] do not count towards the cost, but do fail validation,
    causing the group to fail.

This patch changes validate_event so that it ignores events in the
PERF_EVENT_STATE_OFF state or that are scheduled for other PMUs.
Reported-by: NPawel Moll <pawel.moll@arm.com>
Acked-by: NJamie Iles <jamie.iles@picochip.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

CPU_32v6K is selected by CPU_V7 but it only depends on CPU_V6.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

fixes the warning:
.config:369:warning: symbol value '' invalid for ZRELADDR

and the prompt for ZRELADDR on make
Signed-off-by: NErik Gilling <konkers@android.com>

The 2.6.36-rc kernel added three new system calls:
fanotify_init, fanotify_mark, and prlimit64.  This patch
wires them up on ARM.

The only non-trivial issue here is the u64 argument to
sys_fanotify_mark(), but it is the 3rd argument and thus
passed in r2/r3 in both kernel and user space, so it causes
no problems.

Tested with a 2.6.36-rc2 EABI kernel on an ixp4xx machine.
Tested-by: NAnand Gadiyar <gadiyar@ti.com>
Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This is purely a cosmetic change to the ARM perf backend because the current
comments about the relationship between NMIs, interrupt context and
perf_event_do_pending are misleading.

This patch updates the comments so that they reflect what the code
actually does (which is in line with other architectures).
Acked-by: NJamie Iles <jamie.iles@picochip.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This fixes the compiler warning:

	arch/arm/plat-pxa/pwm.c: In function 'pwm_probe':
	arch/arm/plat-pxa/pwm.c:179: warning: initialization discards qualifiers from pointer target type
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

According to PXA3xx Processor Family Developer Manuall Vol1. section
"Pin Descriptions and Control", PXA30x and PXA31x Processor Alternate
Function Table shows the Alt FN 0 for GPIO51 is CI_HSYNC and for GPIO52
is CI_VSYNC.  This patch fixes the MFP defines and also corrects the
order of MFD defines.
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This is causing section mismatches when linking, as cpufreq_driver->init()
is not supposed to be in init section.
Reported-by: NTomáš 'Sleep_Walker' Čech <sleep_walker@suse.cz>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Following occurs on boot message without this patch.
    CPU1: processor failed to boot
    Brought up 1 CPUs
    SMP: Total of 1 processors activated...

This patch adds SYSRAM mapping for fixing Secondary CPU startup.
    CPU1: Booted secondary processor
    Brought up 2 CPUs
    SMP: Total of 2 processors activated...
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch fixes on enable and ctrlbit of uclk1 and sclk_pwm.
Signed-off-by: NJongpill Lee <boyko.lee@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds missed uart clocks for S5PV310/S5PC210.
Signed-off-by: NJongpill Lee <boyko.lee@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds clk_sclk_apll so that fixes on clk_mout_apll.
Signed-off-by: NJongpill Lee <boyko.lee@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch fixes on PLL setting for S5PV310/S5PC210.
Signed-off-by: NJongpill Lee <boyko.lee@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds CMU block for S5PV310/S5PC210 clock.
(CMU: Clock Management Unit)
Of course, changed current clock addresses for it together.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch fixes typo 'IRQ_WTD' in the irqs.h of S5PV310.
And minor update comments.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds default zreladdr of ARCH_S5PV310.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The S5PV310/S5PC210 has following three GPIO base addresses.

Part1 Base Address=0x11400000
Part2 Base Address=0x11000000
Part3 Base Address=0x03860000
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor edit of title]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Fix this warning:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:644: warning: format '%08lx' expects type
'long unsigned int', but argument 12 has type 'unsigned int'

And removes the useless parens and white space.
Reported-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>

The build failure was introduced by

	13dd0c97 (USB: otg/ulpi: extend the generic ulpi driver.)
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
Cc: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Silences following build warning:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:644: warning: format '%08lx' expects type 'long
unsigned int', but argument 12 has type 'unsigned int'
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Silences following build warning:

arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:644: warning: format '%08lx' expects type 'long
unsigned int', but argument 12 has type 'unsigned int'
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@google.com>

The patch "ARM: Remove DISCONTIGMEM support" removed the node id from
the meminfo struct and the PHYS_TO_NID macro, causing compilation errors:

arch/arm/mach-tegra/board-harmony.c: In function 'tegra_harmony_fixup':
arch/arm/mach-tegra/board-harmony.c:94: error: 'struct membank' has no member named 'node'
arch/arm/mach-tegra/board-harmony.c:94: error: implicit declaration of function 'PHYS_TO_NID'
arch/arm/mach-tegra/board-harmony.c:97: error: 'struct membank' has no member named 'node'
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@google.com>

The core of i.MX5 series is cortex-A8, its cache line size is 64 bytes
instead of 32 bytes. Refer to the OMAP3's selection, we choose 64
bytes for i.MX5, this can increase a little bit performance when
perform cache operations.
Signed-off-by: NJason Wang <jason77.wang@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

We can see MXC_CCM_CCGRx_MOD_OFF is defined as 0 while
MXC_CCM_CCGRx_CG_MASK is defined as 0x3 in crm_regs.h, here in the
_clk_ccgr_disable function, we want to clear the corresponding enable
bit fields to disable this clock, so we should choose MASK instead of
OFF otherwise clocks can't be disabled.
Signed-off-by: NJason Wang <jason77.wang@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>