Both S3C2443 and S3C2416 support 4 UART channels, this patch adds support
for the missing uart channel.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

There are few functions marked as __init, but exported to modules in
devices declaration files.

s3c_nand_set_platdata() and s3c24xx_ts_set_platdata() are used only by
boards init code now, so remove EXPORT_SYMBOL() for them.
Signed-off-by: NYauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

S3C2443 has two-bits pull-up/pull-down configuration fields in GPIO
registers, but values are differ from other SoCs with two-bits
configuration. gpio-cfg-helpers.h already has prototypes for
s3c2443-style pull-up/down methods, so implement them.
Signed-off-by: NYauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Enable card detect by GPIO pin on hsmmc1 device (SD0 on SMDK2416 board)
and enable card polling on hsmmc0 (SD1).
Signed-off-by: NYauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Samsung S3C2416 has two SDHCI controllers compatible with other
Samsung's SoCs (S3C64XX, S5PC100 etc...).

Add required platform setup code that the devices can be used with
sdhci-s3c driver.
Signed-off-by: NYauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
[kgene.kim@samsung.com: change to __raw_{readl,writel} from {readl,writel}]
[kgene.kim@samsung.com: build error fixes]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Define maps for HSMMC devices.

S3C2443 has one HSMMC device with base address 0x4A800000.
S3C2416 has HSMMC0 at 0x4AC00000 and HSMMC1 at 0x4A800000.

So suppose that S3C2443 has only HSMMC1.

Define clock for hsmmc0 device and register it.
Signed-off-by: NYauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using and cleanups
the return of s3c24xx_register_clocks() because it includes it.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using and cleanups
the return of s3c24xx_register_clocks() because it includes it.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The stop function sets the DMA_HALT bit, which prevents
the DMA transfer to resume after stop, for example during
audio PAUSE/PLAY cycle. Clear the HALT bit during start.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

When GENERIC_HARDIRQS_NO_DEPRECATED is enabled, a number of struct
irq_desc members stop being directly accessible, and need to be
accessed via the irq_data struct instead -- this patch fixes up the
plat-samsung sites that still access those members directly.
Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
[kgene.kim@samsung.com: coding-style fixes]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

There may be up to two MIPI CSI slave interfaces depending on the SoC version.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add IRQ and register base address definitions for MIPI CSI slave devices.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Naming changed for consistency with s5pv310 where there are two instances
of the device.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds DM9000 Ethernet Controller device support for SMDKV210.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds the SROM controller clock to the list of clocks to be enabled at
boot time. It is required to be enabled at boot time since the modules connected
over the SROM interface such as the Ethernet controller need an operational SROM.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch modifies the following.

1. Moves the SROM controller mapping from S5PV210 specific code to
   S5P common code. The SROM controller mapping can be used for all
   S5P SoCs.

2. Define the SROM controller physical address for S5P64X0, S5P6442,
   S5PC100, S5PV210 and S5PV310.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Some of the S5P platforms like S5PC100 and S5PV210 include SROM banks
4 and 5 in addition to SROM banks 0 to 3. This patch adds register
offsets for SROM bank 4 and 5.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds shift macros for the SROM Bus width and control
register to represent the shift count for the 5th and 6th SROM
banks.  Some of the S5P SOCs have them.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The SROM register difinitions of S5PV310/S5PC210 (mach/regs-srom.h)
can be used to other S5P SoCs such as S5PV210/S5PC110. So moved into
plat/regs-srom.h of plat-s5p directory.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Change the name of mmc spcial clock from mmc_bus to sclk_mmc to be
in line with the naming across the S5P SoCs
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
[kgene.kim@samsung.com: minor edit of title]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes the gpiolib initialization from arch_initcall
to core_initcall will allow us to make use of gpio functions in
smdk64x0_machine_init function.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds RTC clock for S5P6450.
Signed-off-by: NAtul Dahiya <atul.dahiya@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch renames S5P64X0 GPIOlib file according to other S5P SoCs.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch changes S5P6440 and S5P6450 GPIOlib adding 2bit chips.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds samsung_gpiolib_add_2bit_chips() for cleanup regarding
GPIOlib adding 2bit chips.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Already can support S5P6440 GPIOlib but S5P6450. This patch changes regarding
S5P6440 GPIO definitions so that can be used it from S5P6450 and adds S5P6450
GPIO chips.
Tested-by: NAtul Dahiya <atul.dahiya@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Enable frame buffer display support for SMDKV210 board.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NJonghun Han <jonghun.han@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Universal (C210) board has 3 SDHCI devices.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor edit of title]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support Power Domain for S5PV310 and S5PC210.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch is applied according to the commit 1a8e41cd
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).

Actually, S5PV310 has same cache controller(PL310).

Following is from Catalin Marinas' commit.

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch implements Power Domain control based on Runtime PM framework.
Each Power Domain is represented by a Power Domain device and the devices
belong to these Power Domains should be set as a child device of the Power
Domain devices. The corresponding drivers of the devices should implement
Runtime PM to control the Power Domains.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Conver the VIC timer interrupts to use the irq_ versions of the IRQ
operatiosn introduced in 2.6.37, storing the mask for the timer
interrupt in the chip_data of the irq_data in order to save having to
do a substraction and a shift on every operation.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Convert to the new irq_ versions of the IRQ operations. As well as
the textual substituion of irq_data for the raw IRQ number we also
convert the register base lookup to in s3c_irq_uart_base() to pick
the irq_data up directly.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>