1. 20 4月, 2013 1 次提交
    • D
      sparc64: Fix race in TLB batch processing. · f36391d2
      David S. Miller 提交于
      As reported by Dave Kleikamp, when we emit cross calls to do batched
      TLB flush processing we have a race because we do not synchronize on
      the sibling cpus completing the cross call.
      
      So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
      and either flushes are missed or flushes will flush the wrong
      addresses.
      
      Fix this by using generic infrastructure to synchonize on the
      completion of the cross call.
      
      This first required getting the flush_tlb_pending() call out from
      switch_to() which operates with locks held and interrupts disabled.
      The problem is that smp_call_function_many() cannot be invoked with
      IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
      
      We get the batch processing outside of locked IRQ disabled sections by
      using some ideas from the powerpc port. Namely, we only batch inside
      of arch_{enter,leave}_lazy_mmu_mode() calls.  If we're not in such a
      region, we flush TLBs synchronously.
      
      1) Get rid of xcall_flush_tlb_pending and per-cpu type
         implementations.
      
      2) Do TLB batch cross calls instead via:
      
      	smp_call_function_many()
      		tlb_pending_func()
      			__flush_tlb_pending()
      
      3) Batch only in lazy mmu sequences:
      
      	a) Add 'active' member to struct tlb_batch
      	b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
      	c) Set 'active' in arch_enter_lazy_mmu_mode()
      	d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
      	e) Check 'active' in tlb_batch_add_one() and do a synchronous
                 flush if it's clear.
      
      4) Add infrastructure for synchronous TLB page flushes.
      
      	a) Implement __flush_tlb_page and per-cpu variants, patch
      	   as needed.
      	b) Likewise for xcall_flush_tlb_page.
      	c) Implement smp_flush_tlb_page() to invoke the cross-call.
      	d) Wire up global_flush_tlb_page() to the right routine based
                 upon CONFIG_SMP
      
      5) It turns out that singleton batches are very common, 2 out of every
         3 batch flushes have only a single entry in them.
      
         The batch flush waiting is very expensive, both because of the poll
         on sibling cpu completeion, as well as because passing the tlb batch
         pointer to the sibling cpus invokes a shared memory dereference.
      
         Therefore, in flush_tlb_pending(), if there is only one entry in
         the batch perform a completely asynchronous global_flush_tlb_page()
         instead.
      Reported-by: NDave Kleikamp <dave.kleikamp@oracle.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Acked-by: NDave Kleikamp <dave.kleikamp@oracle.com>
      f36391d2
  2. 19 4月, 2013 1 次提交
    • R
      ARM: highbank: fix cache flush ordering for cpu hotplug · 73053d97
      Rob Herring 提交于
      The L1 data cache flush needs to be after highbank_set_cpu_jump call which
      pollutes the cache with the l2x0_lock. This causes other cores to deadlock
      waiting for the l2x0_lock. Moving the flush of the entire data cache after
      highbank_set_cpu_jump fixes the problem. Use flush_cache_louis instead of
      flush_cache_all are that is sufficient to flush only the L1 data cache.
      flush_cache_louis did not exist when highbank_cpu_die was originally
      written.
      
      With PL310 errata 769419 enabled, a wmb is inserted into idle which takes
      the l2x0_lock. This makes the problem much more easily hit and causes
      reset to hang.
      Reported-by: NPaolo Pisati <p.pisati@gmail.com>
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      73053d97
  3. 18 4月, 2013 2 次提交
  4. 17 4月, 2013 3 次提交
  5. 15 4月, 2013 2 次提交
    • K
      powerpc: add a missing label in resume_kernel · d8b92292
      Kevin Hao 提交于
      A label 0 was missed in the patch a9c4e541 (powerpc/kprobe: Complete
      kprobe and migrate exception frame). This will cause the kernel
      branch to an undetermined address if there really has a conflict when
      updating the thread flags.
      Signed-off-by: NKevin Hao <haokexin@gmail.com>
      Cc: stable@vger.kernel.org
      Acked-By: NTiejun Chen <tiejun.chen@windriver.com>
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      d8b92292
    • A
      powerpc: Fix audit crash due to save/restore PPR changes · 05e38e5d
      Alistair Popple 提交于
      The current mainline crashes when hitting userspace with the following:
      
      kernel BUG at kernel/auditsc.c:1769!
      cpu 0x1: Vector: 700 (Program Check) at [c000000023883a60]
          pc: c0000000001047a8: .__audit_syscall_entry+0x38/0x130
          lr: c00000000000ed64: .do_syscall_trace_enter+0xc4/0x270
          sp: c000000023883ce0
         msr: 8000000000029032
        current = 0xc000000023800000
        paca    = 0xc00000000f080380   softe: 0        irq_happened: 0x01
          pid   = 1629, comm = start_udev
      kernel BUG at kernel/auditsc.c:1769!
      enter ? for help
      [c000000023883d80] c00000000000ed64 .do_syscall_trace_enter+0xc4/0x270
      [c000000023883e30] c000000000009b08 syscall_dotrace+0xc/0x38
       --- Exception: c00 (System Call) at 0000008010ec50dc
      
      Bisecting found the following patch caused it:
      
      commit 44e9309f
      Author: Haren Myneni <haren@linux.vnet.ibm.com>
      powerpc: Implement PPR save/restore
      
      It was found this patch corrupted r9 when calling
      SET_DEFAULT_THREAD_PPR()
      
      Using r10 as a scratch register instead of r9 solved the problem.
      Signed-off-by: NAlistair Popple <alistair@popple.id.au>
      Acked-by: NMichael Neuling <mikey@neuling.org>
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      05e38e5d
  6. 13 4月, 2013 1 次提交
    • D
      x86-32: Fix possible incomplete TLB invalidate with PAE pagetables · 1de14c3c
      Dave Hansen 提交于
      This patch attempts to fix:
      
      	https://bugzilla.kernel.org/show_bug.cgi?id=56461
      
      The symptom is a crash and messages like this:
      
      	chrome: Corrupted page table at address 34a03000
      	*pdpt = 0000000000000000 *pde = 0000000000000000
      	Bad pagetable: 000f [#1] PREEMPT SMP
      
      Ingo guesses this got introduced by commit 611ae8e3 ("x86/tlb:
      enable tlb flush range support for x86") since that code started to free
      unused pagetables.
      
      On x86-32 PAE kernels, that new code has the potential to free an entire
      PMD page and will clear one of the four page-directory-pointer-table
      (aka pgd_t entries).
      
      The hardware aggressively "caches" these top-level entries and invlpg
      does not actually affect the CPU's copy.  If we clear one we *HAVE* to
      do a full TLB flush, otherwise we might continue using a freed pmd page.
      (note, we do this properly on the population side in pud_populate()).
      
      This patch tracks whenever we clear one of these entries in the 'struct
      mmu_gather', and ensures that we follow up with a full tlb flush.
      
      BTW, I disassembled and checked that:
      
      	if (tlb->fullmm == 0)
      and
      	if (!tlb->fullmm && !tlb->need_flush_all)
      
      generate essentially the same code, so there should be zero impact there
      to the !PAE case.
      Signed-off-by: NDave Hansen <dave.hansen@linux.intel.com>
      Cc: Peter Anvin <hpa@zytor.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Artem S Tashkinov <t.artem@mailcity.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      1de14c3c
  7. 12 4月, 2013 2 次提交
  8. 11 4月, 2013 9 次提交
  9. 10 4月, 2013 4 次提交
  10. 09 4月, 2013 8 次提交
    • S
      ARM: S3C24XX: Fix interrupt pending register offset of the EINT controller · 646dd2f0
      Sylwester Nawrocki 提交于
      The external pending interrupt register address (EINTPEND) offset is
      0xa8, not 0x08. Without this patch the external interrupts are not
      properly acknowledged, which may lead to an interrupt storm and the
      system hang as soon as any external interrupt is requested.
      Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
      Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      646dd2f0
    • S
      ARM: S3C24XX: Correct NR_IRQS definition for s3c2440 · b530f742
      Sylwester Nawrocki 提交于
      Due to NR_IRQS being incorrectly defined not all IRQ domains can
      be registered for S3C2440. It causes following errors on a s3c2440
      SoC based board:
      
      NR_IRQS:89
      S3C2440: IRQ Support
      irq: clearing pending status 00000002
      ------------[ cut here ]------------
      WARNING: at kernel/irq/irqdomain.c:234 0xc0056ed0()
      ...
      irq: could not create irq-domain
      ...
      s3c2410-wdt s3c2410-wdt: failed to install irq (-22)
      s3c2410-wdt: probe of s3c2410-wdt failed with error -22
      ...
      samsung-uart s3c2440-uart.0: cannot get irq 74
      
      Fix this by increasing NR_IRQS to at least (IRQ_S3C2443_AC97 + 1)
      if CPU_S3C2440 is selected, so the subintc IRQ domain gets properly
      registered.
      Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
      Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
      Acked-by: NHeiko Stuebner <heiko@sntech.de>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      b530f742
    • D
      ARM i.MX6: Fix ldb_di clock selection · e8094b2c
      Dirk Behme 提交于
      According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
      of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
      the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
      clock is named 'pll3_usb_otg', select this instead of the 540M clock.
      Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      e8094b2c
    • S
      ARM: imx: provide twd clock lookup from device tree · 2bb4b70b
      Shawn Guo 提交于
      While booting from device tree, imx6q used to provide twd clock lookup
      by calling clk_register_clkdev() in clock driver.  However, the commit
      bd603455 (ARM: use device tree to get smp_twd clock) forces DT boot to
      look up the clock from device tree.  It causes the failure below when
      twd driver tries to get the clock, and hence kernel has to calibrate the
      local timer frequency.
      
       smp_twd: clock not found -2
       ...
       Calibrating local timer... 396.13MHz.
      
      Fix the regression by providing twd clock lookup from device tree, and
      remove the unused twd clk_register_clkdev() call from clock driver.
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      2bb4b70b
    • M
      ARM: imx35 Bugfix admux clock · 75498083
      Markus Pargmann 提交于
      The admux clock seems to be the audmux clock as tests show. audmux does
      not work without this clock enabled. Currently imx35 does not register a
      clock device for audmux. This patch adds this registration. imx-audmux
      driver already handles a clock device, so no changes are necessary
      there.
      Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
      Cc: stable@vger.kernel.org
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      75498083
    • M
      ARM: clk-imx35: Bugfix iomux clock · cab1e0a3
      Markus Pargmann 提交于
      This patch enables iomuxc_gate clock. It is necessary to be able to
      reconfigure iomux pads. Without this clock enabled, the
      clk_disable_unused function will disable this clock and the iomux pads
      are not configurable anymore. This happens at every boot. After a reboot
      (watchdog system reset) the clock is not enabled again, so all iomux pad
      reconfigurations in boot code are without effect.
      
      The iomux pads should be always configurable, so this patch always
      enables it.
      Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
      Cc: stable@vger.kernel.org
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      cab1e0a3
    • G
      m68k: define a local gpio_request_one() function · b2dfaa8d
      Greg Ungerer 提交于
      Compiling for linux-3.9-rc1 and later fails with:
      
      drivers/gpio/devres.c: In function 'devm_gpio_request_one':
      drivers/gpio/devres.c:90:2: error: implicit declaration of function 'gpio_request_one' [-Werror=implicit-function-declaration]
      
      So provide a local gpio_request_one() function. Code largely borrowed from
      blackfin's local gpio_request_one() function.
      Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      b2dfaa8d
    • C
      ARC: Add implicit compiler barrier to raw_local_irq* functions · 79e5f05e
      Christian Ruppert 提交于
      ARC irqsave/restore macros were missing the compiler barrier, causing a
      stale load in irq-enabled region be used in irq-safe region, despite
      being changed, because the register holding the value was still live.
      
      The problem manifested as random crashes in timer code when stress
      testing ARCLinux (3.9-rc3) on a !SMP && !PREEMPT_COUNT
      
      Here's the exact sequence which caused this:
       (0). tv1[x] <----> t1 <---> t2
       (1). mod_timer(t1) interrupted after it calls timer_pending()
       (2). mod_timer(t2) completes
       (3). mod_timer(t1) resumes but messes up the list
       (4). __runt_timers( ) uses bogus timer_list entry / crashes in
            timer->function
      
      Essentially mod_timer() was racing against itself and while the spinlock
      serialized the tv1[] timer link list, timer_pending() called outside the
      spinlock, cached timer link list element in a register.
      With low register pressure (and a deep register file), lack of barrier
      in raw_local_irqsave() as well as preempt_disable (!PREEMPT_COUNT
      version), there was nothing to force gcc to reload across the spinlock,
      causing a stale value in reg be used for link list manipulation - ensuing
      a corruption.
      
      ARcompact disassembly which shows the culprit generated code:
      
      mod_timer:
          push_s blink
          mov_s r13,r0	# timer, timer
      ..
          ###### timer_pending( )
          ld_s r3,[r13]       # <------ <variable>.entry.next LOADED
          brne r3, 0, @.L163
      
      .L163:
      ..
          ###### spin_lock_irq( )
          lr  r5, [status32]  # flags
          bic r4, r5, 6       # temp, flags,
          and.f 0, r5, 6      # flags,
          flag.nz r4
      
          ###### detach_if_pending( ) begins
      
          tst_s r3,r3  <--------------
      			# timer_pending( ) checks timer->entry.next
                              # r3 is NOT reloaded by gcc, using stale value
          beq.d @.L169
          mov.eq r0,0
      
          #####  detach_timer( ): __list_del( )
      
          ld r4,[r13,4]    	# <variable>.entry.prev, D.31439
          st r4,[r3,4]     	# <variable>.prev, D.31439
          st r3,[r4]       	# <variable>.next, D.30246
      
      We initially tried to fix this by adding barrier() to preempt_* macros
      for !PREEMPT_COUNT but Linus clarified that it was anything but wrong.
      http://www.spinics.net/lists/kernel/msg1512709.html
      
      [vgupta: updated commitlog]
      
      Reported-by/Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
      Cc: Christian Ruppert <christian.ruppert@abilis.com>
      Cc: Pierrick Hascoet <pierrick.hascoet@abilis.com>
      Debugged-by/Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      79e5f05e
  11. 08 4月, 2013 6 次提交
  12. 07 4月, 2013 1 次提交