1. 17 7月, 2014 1 次提交
  2. 13 7月, 2014 4 次提交
  3. 12 7月, 2014 1 次提交
  4. 11 7月, 2014 1 次提交
  5. 07 7月, 2014 1 次提交
  6. 04 7月, 2014 1 次提交
  7. 30 6月, 2014 1 次提交
  8. 29 6月, 2014 1 次提交
    • T
      ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache · 98ea2dba
      Thomas Petazzoni 提交于
      When a PL310 cache is used on a system that provides hardware
      coherency, the outer cache sync operation is useless, and can be
      skipped. Moreover, on some systems, it is harmful as it causes
      deadlocks between the Marvell coherency mechanism, the Marvell PCIe
      controller and the Cortex-A9.
      
      To avoid this, this commit introduces a new Device Tree property
      'arm,io-coherent' for the L2 cache controller node, valid only for the
      PL310 cache. It identifies the usage of the PL310 cache in an I/O
      coherent configuration. Internally, it makes the driver disable the
      outer cache sync operation.
      
      Note that technically speaking, a fully coherent system wouldn't
      require any of the other .outer_cache operations. However, in
      practice, when booting secondary CPUs, these are not yet coherent, and
      therefore a set of cache maintenance operations are necessary at this
      point. This explains why we keep the other .outer_cache operations and
      only ->sync is disabled.
      
      While in theory any write to a PL310 register could cause the
      deadlock, in practice, disabling ->sync is sufficient to workaround
      the deadlock, since the other cache maintenance operations are only
      used in very specific situations.
      
      Contrary to previous versions of this patch, this new version does not
      simply NULL-ify the ->sync member, because the l2c_init_data
      structures are now 'const' and therefore cannot be modified, which is
      a good thing. Therefore, this patch introduces a separate
      l2c_init_data instance, called of_l2c310_coherent_data.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      98ea2dba
  9. 25 6月, 2014 3 次提交
  10. 24 6月, 2014 5 次提交
  11. 22 6月, 2014 1 次提交
    • A
      spi: qup: Remove chip select function · 4a8573ab
      Andy Gross 提交于
      This patch removes the chip select function.  Chip select should instead be
      supported using GPIOs, defining the DT entry "cs-gpios", and letting the SPI
      core assert/deassert the chip select as it sees fit.
      
      The chip select control inside the controller is buggy.  It is supposed to
      automatically assert the chip select based on the activity in the controller,
      but it is buggy and doesn't work at all.  So instead we elect to use GPIOs.
      Signed-off-by: NAndy Gross <agross@codeaurora.org>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      4a8573ab
  12. 19 6月, 2014 2 次提交
  13. 17 6月, 2014 4 次提交
  14. 13 6月, 2014 2 次提交
  15. 12 6月, 2014 5 次提交
  16. 11 6月, 2014 5 次提交
  17. 10 6月, 2014 2 次提交