Linux on Vybrid used several different L2 latencies so far, none
of them seem to be the right ones. According to the application note
AN4947 ("Understanding Vybrid Architecture"), the tag portion runs
on CPU clock and is inside the L2 cache controller, whereas the data
portion is stored in the external SRAM running on platform clock.
Hence it is likely that the correct value requires a higher data
latency then tag latency.

These are the values which have been used so far:
- The mainline values:
  arm,data-latency = <1 1 1>;
  arm,tag-latency = <2 2 2>;
  Those values have lead to problems on higher clocks. They look
  like a poor translation from the reset values (missing +1 offset
  and a mix up between tag/latency values).
- The Linux 3.0 (SoC vendor BSP) values (converted to DT notation):
  arm,data-latency = <4 2 3>
  arm,tag-latency = <4 2 3>
  The cache initialization function along with the value matches the
  i.MX6 code from the same kernel, so it seems that those values have
  just been copied.
- The Colibri values:
  arm,data-latency = <2 1 2>;
  arm,tag-latency = <3 2 3>;
  Those were a mix between the values of the Linux 3.0 based BSP and
  the mainline values above.
- The SoC Reset values (converted to DT notation):
  arm,data-latency = <3 3 3>;
  arm,tag-latency = <2 2 2>;

So far there is no official statement on what the correct values are.
See also the related Freescale community thread:
https://community.freescale.com/message/579785#579785

For now, the reset values seem to be the best bet. Remove all other
"bogus" values and use the reset value on vf610.dtsi level.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Cc: <stable@vger.kernel.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This adds more generic base device trees for Vybrid SoCs. There
are three series of Vybrid SoC commonly available:
- VF3xx series: single core, Cortex-A5 without external memory
- VF5xx series: single core, Cortex-A5
- VF6xx series: dual core, Cortex-A5/Cortex-M4

The second digit represents the presents of a L2 cache (VFx1x).

The VF3xx series are not suitable for Linux especially since the
internal memory is quite small (1.5MiB).

The VF500 is essentially the base SoC, with only one core and
without L1 cache. The VF610 is a superset of the VF500, hence
vf500.dtsi is then included and enhanced by vf610.dtsi. There is
no board using VF510 or VF600 currently, but, if needed, they can
be added easily.

The Linux kernel can also run on the Cortex-M4 CPU of Vybrid
using !MMU support. This patchset creates a device tree structure
which allows to share peripherals nodes for a VF6xx Cortex-M4
device tree too. The two CPU types have different views of the
system: Foremost they are using different interrupt controllers,
but also the memory map is slightly different. The base device
tree vfxxx.dtsi allows to create SoC and board level device trees
supporting the Cortex-M4 while reusing the shared peripherals
nodes.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The clock controller module (CCM) has several clock inputs, which
are connected to external crystal oscillators. To reflect this,
assign these fixed clocks to the CCM node directly.

This especially resolves initialization order dependencies we had
with the earlier initialization code: When resolving of the fixed
clocks failed in clk-vf610, the code created fixed clocks with a
rate of 0.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add Global Timer support which is part of the private peripherals
of the Cortex-A5 processor. This Global Timer is compatible with the
Cortex-A9 implementation. It's a 64-bit timer and is clocked by the
peripheral clock, which is typically 133 or 166MHz on Vybrid.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Acked-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add device tree node for usbmisc which controls the non-core USB
registers. This is required to use the property to disable the over-
current detection.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This adds USB PHY and USB controller nodes. Vybrid SoCs have two
independent USB cores which each supports DR (dual role). However,
real OTG is not supported since the OTG ID pin is not available.

The PHYs are located within the anadig register range, hence we need
to change the length of the anadig registers.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add FlexCAN node for the two FlexCAN IP instances in Vybrid.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This adds devicetree node for VF610, and there are 8 channels
supported.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NYuan Yao <yao.yuan@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The kernel was not able to boot from SD card because sdhc support
was not present into the dts.

A new entry for sdhc1 was added for vf610-twr board based on the
compatible entry present on imx53.

After applying these changes, the kernel is able to boot successfully
from SD card.
Signed-off-by: NCosmin Stoica <cosminstefan.stoica@freescale.com>
Signed-off-by: NChircu Bogdan <Bogdan.Chircu@freescale.com>
Signed-off-by: NEddy Petrisor <eddy.petrisor@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Per bindings of fixed-clock, #clock-cells is a required property.  Let's
add it for those fixed rate clocks.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This is likely a copy-and-paste error from the
ARM GIC documentation, that has already been fixed.

address-cells should have been set to 0, as with the size
cells. As having those properties set to 0 is the
same thing as not specifying them, drop them completely.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add i2c dts node properties for eDMA support, them depend on the eDMA driver.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

vf610 has two ADC controllers, and vf610-twr board ADC0_SE5 pin connect
to sliding rheostat for ADC test, other ADC pins connect to connectors for
future use.

Add support for ADC0_SE5.

CC: Jonathan Cameron <jic23@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: Peter Meerwald <pmeerw@pmeerw.net>
CC: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch adds the SAI's edma mux Tx and Rx support.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add lpuart dts node properties for eDMA support, them depend on the eDMA driver.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NJingchang Lu <b35083@freescale.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace
the hardcode.

[shawn.guo: While at it, we also fix the typo in uart0 interrupts
property, where the 0x00 should 0x04.  Hense, it should also be
IRQ_TYPE_LEVEL_HIGH just like other UART instances.]
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts.  However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected.  This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board.  It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.

The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral.  Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NFugang Duan <B38611@freescale.com>

Add Freescale DSPI node into vf610 dts.
Signed-off-by: NChao Fu <b44548@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The fec/enet driver calculates MDC rate with the formula below.

  ref_freq / ((MII_SPEED + 1) x 2)

The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now.  And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec.  This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz).  That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz.  And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.

  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half

Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.

Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The gpio-ranges properties in vf610.dtsi were written according to an
older version of the GPIO bindings. Unfortunately, these were changed
incompatibly in commit 86853c83 "gpio: add gpio offset in gpio range
cells property". This patch adds the missing required extra cell in each
gpio-ranges property.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add SoC level device tree source for Freescale Vybrid VF610.
Signed-off-by: NJingchang Lu <b35083@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>