1. 10 3月, 2011 1 次提交
  2. 21 1月, 2011 1 次提交
  3. 09 7月, 2010 1 次提交
  4. 15 6月, 2010 1 次提交
  5. 06 5月, 2010 1 次提交
  6. 30 3月, 2010 1 次提交
    • T
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking... · 5a0e3ad6
      Tejun Heo 提交于
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
      
      percpu.h is included by sched.h and module.h and thus ends up being
      included when building most .c files.  percpu.h includes slab.h which
      in turn includes gfp.h making everything defined by the two files
      universally available and complicating inclusion dependencies.
      
      percpu.h -> slab.h dependency is about to be removed.  Prepare for
      this change by updating users of gfp and slab facilities include those
      headers directly instead of assuming availability.  As this conversion
      needs to touch large number of source files, the following script is
      used as the basis of conversion.
      
        http://userweb.kernel.org/~tj/misc/slabh-sweep.py
      
      The script does the followings.
      
      * Scan files for gfp and slab usages and update includes such that
        only the necessary includes are there.  ie. if only gfp is used,
        gfp.h, if slab is used, slab.h.
      
      * When the script inserts a new include, it looks at the include
        blocks and try to put the new include such that its order conforms
        to its surrounding.  It's put in the include block which contains
        core kernel includes, in the same order that the rest are ordered -
        alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
        doesn't seem to be any matching order.
      
      * If the script can't find a place to put a new include (mostly
        because the file doesn't have fitting include block), it prints out
        an error message indicating which .h file needs to be added to the
        file.
      
      The conversion was done in the following steps.
      
      1. The initial automatic conversion of all .c files updated slightly
         over 4000 files, deleting around 700 includes and adding ~480 gfp.h
         and ~3000 slab.h inclusions.  The script emitted errors for ~400
         files.
      
      2. Each error was manually checked.  Some didn't need the inclusion,
         some needed manual addition while adding it to implementation .h or
         embedding .c file was more appropriate for others.  This step added
         inclusions to around 150 files.
      
      3. The script was run again and the output was compared to the edits
         from #2 to make sure no file was left behind.
      
      4. Several build tests were done and a couple of problems were fixed.
         e.g. lib/decompress_*.c used malloc/free() wrappers around slab
         APIs requiring slab.h to be added manually.
      
      5. The script was run on all .h files but without automatically
         editing them as sprinkling gfp.h and slab.h inclusions around .h
         files could easily lead to inclusion dependency hell.  Most gfp.h
         inclusion directives were ignored as stuff from gfp.h was usually
         wildly available and often used in preprocessor macros.  Each
         slab.h inclusion directive was examined and added manually as
         necessary.
      
      6. percpu.h was updated not to include slab.h.
      
      7. Build test were done on the following configurations and failures
         were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
         distributed build env didn't work with gcov compiles) and a few
         more options had to be turned off depending on archs to make things
         build (like ipr on powerpc/64 which failed due to missing writeq).
      
         * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
         * powerpc and powerpc64 SMP allmodconfig
         * sparc and sparc64 SMP allmodconfig
         * ia64 SMP allmodconfig
         * s390 SMP allmodconfig
         * alpha SMP allmodconfig
         * um on x86_64 SMP allmodconfig
      
      8. percpu.h modifications were reverted so that it could be applied as
         a separate patch and serve as bisection point.
      
      Given the fact that I had only a couple of failures from tests on step
      6, I'm fairly confident about the coverage of this conversion patch.
      If there is a breakage, it's likely to be something in one of the arch
      headers which should be easily discoverable easily on most builds of
      the specific arch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
      5a0e3ad6
  7. 19 2月, 2010 1 次提交
  8. 09 2月, 2010 1 次提交
  9. 18 12月, 2009 1 次提交
  10. 09 12月, 2009 1 次提交
  11. 24 11月, 2009 1 次提交
  12. 30 10月, 2009 1 次提交
  13. 20 8月, 2009 1 次提交
  14. 08 7月, 2009 1 次提交
    • A
      powerpc: Don't use alloc_bootmem() in init_IRQ() path · ea96025a
      Anton Vorontsov 提交于
      This patch fixes various badnesses like this for all interrupt
      controllers:
      
      ------------[ cut here ]------------
      Badness at c04db9dc [verbose debug info unavailable]
      NIP: c04db9dc LR: c04db9ac CTR: 00000000
      REGS: c053de30 TRAP: 0700   Not tainted  (2.6.31-rc1-00432-ge69b2b5-dirty)
      MSR: 00021000 <ME,CE>  CR: 22020084  XER: 00000000
      TASK = c0500480[0] 'swapper' THREAD: c053c000
      GPR00: 00000001 c053dee0 c0500480 00000000 00000050 00000020 3fffffff 00000000
      GPR08: 00000001 c0540000 e0080080 00000000 22000084 64183600 3ff8f800 00000000
      GPR16: 841b0240 449a0303 00000000 00000000 00000000 00000000 00000000 c04f5bf4
      GPR24: 00000000 00000000 00000000 00000050 00000020 00000000 3fffffff 00000050
      NIP [c04db9dc] alloc_arch_preferred_bootmem+0x48/0x74
      LR [c04db9ac] alloc_arch_preferred_bootmem+0x18/0x74
      Call Trace:
      [c053dee0] [c000a5a4] __of_address_to_resource+0x44/0xd0 (unreliable)
      [c053def0] [c04dba58] ___alloc_bootmem_nopanic+0x50/0x108
      [c053df20] [c04dbb28] ___alloc_bootmem+0x18/0x50
      [c053df30] [c04d5de0] qe_ic_init+0x5c/0x1b0
      [c053df70] [c04d77b0] mpc85xx_mds_pic_init+0xb8/0x10c
      [c053dfb0] [c04cf374] init_IRQ+0x28/0x3c
      
      p.s. commit 85355bb2 ("powerpc: Fix
      mpic alloc warning") missed some alloc_bootmem() instances, this is
      now fixed.
      Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
      Acked-by: NTimur Tabi <timur@freescale.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ea96025a
  15. 26 6月, 2009 2 次提交
    • K
      powerpc: Fix mpic alloc warning · 85355bb2
      Kumar Gala 提交于
      Since we can use kmalloc earlier we are getting the following since the
      mpic_alloc() code calls alloc_bootmem().  Move to using kzalloc() to
      remove the warning.
      
      ------------[ cut here ]------------
      Badness at c0583248 [verbose debug info unavailable]
      NIP: c0583248 LR: c0583210 CTR: 00000004
      REGS: c0741de0 TRAP: 0700   Not tainted  (2.6.30-06736-g12a31df)
      MSR: 00021000 <ME,CE>  CR: 22024024  XER: 00000000
      TASK = c070d3b8[0] 'swapper' THREAD: c0740000 CPU: 0
      <6>GPR00: 00000001 c0741e90 c070d3b8 00000001 00000210 00000020 3fffffff 00000000
      <6>GPR08: 00000000 c0c85700 c04f8c40 0000002d 22044022 1004a388 7ffd9400 00000000
      <6>GPR16: 00000000 7ffcd100 7ffcd100 7ffcd100 c04f8c40 00000000 c059f62c c075a0c0
      <6>GPR24: c059f648 00000000 0000000f 00000210 00000020 00000000 3fffffff 00000210
      NIP [c0583248] alloc_arch_preferred_bootmem+0x50/0x80
      LR [c0583210] alloc_arch_preferred_bootmem+0x18/0x80
      Call Trace:
      [c0741e90] [c07343b0] devtree_lock+0x0/0x24 (unreliable)
      [c0741ea0] [c0583b14] ___alloc_bootmem_nopanic+0x54/0x108
      [c0741ee0] [c0583e18] ___alloc_bootmem+0x18/0x50
      [c0741ef0] [c057b9cc] mpic_alloc+0x48/0x710
      [c0741f40] [c057ecf4] mpc85xx_ds_pic_init+0x190/0x1b8
      [c0741f90] [c057633c] init_IRQ+0x24/0x34
      [c0741fa0] [c05738b8] start_kernel+0x260/0x3dc
      [c0741ff0] [c00003c8] skpinv+0x2e0/0x31c
      Instruction dump:
      409e001c 7c030378 80010014 83e1000c 38210010 7c0803a6 4e800020 3d20c0c8
      39295700 80090004 7c000034 5400d97e <0f000000> 2f800000 409e001c 38800000
      
      BenH: Changed to use GFP_KERNEL, the allocator will do the right thing
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      85355bb2
    • B
      powerpc/mpic: Fix mapping of "DCR" based MPIC variants · 5a2642f6
      Benjamin Herrenschmidt 提交于
      Commit 31207dab
      "Fix incorrect allocation of interrupt rev-map"
      introduced a regression crashing on boot on machines using
      a "DCR" based MPIC, such as the Cell blades.
      
      The reason is that the irq host data structure is initialized
      much later as a result of that patch, causing our calls to
      mpic_map() do be done before we have a host setup.
      
      Unfortunately, this breaks _mpic_map_dcr() which uses the
      mpic->irqhost to get to the device node.
      
      This fixes it by, instead, passing the device node explicitely
      to mpic_map().
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: NAkira Tsukamoto <akirat@rd.scei.sony.co.jp>
      5a2642f6
  16. 21 5月, 2009 1 次提交
  17. 15 5月, 2009 1 次提交
  18. 28 4月, 2009 1 次提交
    • Y
      irq: change ->set_affinity() to return status · d5dedd45
      Yinghai Lu 提交于
      according to Ingo, change set_affinity() in irq_chip should return int,
      because that way we can handle failure cases in a much cleaner way, in
      the genirq layer.
      
      v2: fix two typos
      
      [ Impact: extend API ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: linux-arch@vger.kernel.org
      LKML-Reference: <49F654E9.4070809@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d5dedd45
  19. 06 4月, 2009 1 次提交
  20. 13 1月, 2009 2 次提交
  21. 13 12月, 2008 1 次提交
  22. 03 12月, 2008 1 次提交
  23. 01 12月, 2008 1 次提交
    • A
      powerpc/mpic: Don't reset affinity for secondary MPIC on boot · cc353c30
      Arnd Bergmann 提交于
      Kexec/kdump currently fails on the IBM QS2x blades when the kexec happens
      on a CPU other than the initial boot CPU.  It turns out that this is the
      result of mpic_init trying to set affinity of each interrupt vector to the
      current boot CPU.
      
      As far as I can tell,  the same problem is likely to exist on any
      secondary MPIC, because they have to deliver interrupts to the first
      output all the time. There are two potential solutions for this: either
      not set up affinity at all for secondary MPICs, or assume that a single
      CPU output is connected to the upstream interrupt controller and hardcode
      affinity to that per architecture.
      
      This patch implements the second approach, defaulting to the first output.
      Currently, all known secondary MPICs are routed to their upstream port
      using the first destination, so we hardcode that.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cc353c30
  24. 19 11月, 2008 1 次提交
  25. 31 10月, 2008 1 次提交
  26. 26 6月, 2008 1 次提交
  27. 09 6月, 2008 2 次提交
  28. 23 5月, 2008 2 次提交
  29. 07 4月, 2008 1 次提交
  30. 26 2月, 2008 1 次提交
  31. 25 1月, 2008 1 次提交
  32. 24 1月, 2008 1 次提交
  33. 28 12月, 2007 2 次提交
    • O
      [POWERPC] pasemi: Distribute interrupts evenly across cpus · d87bf3be
      Olof Johansson 提交于
      By default the OpenPIC on PWRficient will bias to one core (since that
      will improve changes of the other core being able to stay idle/powered
      down). However, this conflicts with most irq load balancing schemes,
      since setting an interrupt to be delivered to either core doesn't really
      result in the load being shared. It also doesn't work well with the
      soft irq disable feature of PPC, since EE will stay on until the first
      interrupt is taken while soft disabled.
      
      Set the gconf0 config bit that enables even distribution of interrupts
      among the two cores.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      d87bf3be
    • O
      [POWERPC] pasemi: Implement NMI support · f365355e
      Olof Johansson 提交于
      Some PWRficient-based boards have a NMI button that's wired up to a GPIO
      as interrupt source. By configuring the openpic accordingly, these get
      delivered as a machine check with high priority, instead of as an external
      interrupt.
      
      The device tree contains a property "nmi-source" in the openpic node
      for these systems, and it's the (hwirq) source for the input.
      
      Also, for these interrupts, the IACK is read from another register than
      the regular (MCACK instead), but they are EOI'd as usual. So implement
      said function for the mpic driver.
      
      Finally, move a couple of external function defines to include/ instead
      of local under sysdev. Being able to mask/unmask and eoi directly saves
      us from setting up a dummy irq handler that will never be called.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      f365355e
  34. 20 12月, 2007 2 次提交
    • O
      [POWERPC] pasemi: Implement MSI support · 38958dd9
      Olof Johansson 提交于
      Implement MSI support for PA Semi PWRficient platforms. MSI is done
      through a special range of sources on the openpic controller, and they're
      unfortunately breaking the usual concepts of how sources are programmed:
      
      * The source is calculated as 512 + the value written into the MSI
        register
      * The vector for this source is added to the source and reported
        through IACK
      
      This means that for simplicity, it makes much more sense to just set the
      vector to 0 for the source, since that's really the vector we expect to
      see from IACK.
      
      Also, the affinity/priority registers will affect 16 sources at a
      time. To avoid most (simple) users from being limited by this, allocate
      16 sources per device but use only one. This means that there's a total
      of 32 sources.
      
      If we get usage scenarions that need more sources, the allocator should
      probably be revised to take an alignment argument and size, not just do
      natural alignment.
      
      Finally, since I'm already touching the MPIC names on pasemi, rename
      the base one from the somewhat odd " PAS-OPIC  " to "PASEMI-OPIC".
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      38958dd9
    • O
      [POWERPC] MPIC: Minor optimization of ipi handler · 194046a1
      Olof Johansson 提交于
      Optimize MPIC IPIs, by passing in the IPI number as the argument to the
      handler, since all we did was translate it back based on which mpic
      the interrupt came though on (and that was always the primary mpic).
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      194046a1