1. 31 3月, 2014 1 次提交
  2. 18 11月, 2013 1 次提交
  3. 12 7月, 2013 1 次提交
  4. 20 12月, 2012 1 次提交
  5. 29 11月, 2012 3 次提交
  6. 08 11月, 2012 1 次提交
    • R
      WATCHDOG: fix build PM warnings · 60d6dd53
      Russell King 提交于
      drivers/watchdog/sp805_wdt.c:288:12: warning: 'sp805_wdt_suspend' defined but not used
      drivers/watchdog/sp805_wdt.c:298:12: warning: 'sp805_wdt_resume' defined but not used
      
      This is caused by the wrong config symbol being used for these functions.
      Rather than fixing that, mark the functions with __maybe_unused
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      60d6dd53
  7. 21 6月, 2012 1 次提交
  8. 30 5月, 2012 2 次提交
  9. 28 3月, 2012 5 次提交
  10. 17 3月, 2012 1 次提交
  11. 26 12月, 2011 1 次提交
  12. 22 11月, 2011 1 次提交
  13. 27 7月, 2011 2 次提交
    • N
      watchdog: sp805: Flush posted writes in enable/disable. · 081d83a3
      Nick Bowler 提交于
      There are no reads in these functions, so if MMIO writes are posted,
      the writes in enable/disable may not have completed by the time these
      functions return.  If the functions run from different CPUs, it's
      in theory possible for the writes to be interleaved, which would be
      disastrous for this driver.
      
      At the very least, we need an mmiowb() before releasing the lock, but
      since it seems desirable for the watchdog timer to be actually stopped
      or reset when these functions return, read the lock register to force
      the writes out.
      Signed-off-by: NNick Bowler <nbowler@elliptictech.com>
      Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      081d83a3
    • N
      watchdog: sp805: Don't write 0 to the load value register. · da3e5150
      Nick Bowler 提交于
      At least on the Versatile Express' V2M, calling wdt_disable followed by
      wdt_enable, for instance by running the following sequence:
      
        echo V > /dev/watchdog; echo V > /dev/watchdog
      
      results in an immediate reset.  The wdt_disable function writes 0 to the
      load register; while the watchdog interrupts are disabled at this point,
      this special value is defined to trigger an interrupt immediately.  It
      appears that in this instance, the reset happens when the interrupts
      are subsequently enabled by wdt_enable.
      
      Putting in a short delay after writing a new load value in wdt_enable
      solves the issue, but it seems cleaner to simply never write 0 to the
      load register at all: according to the hardware docs, writing 0 to the
      control register suffices to stop the counter, and the write of 0 to
      the load register is questionable anyway since this register resets to
      0xffffffff.
      Signed-off-by: NNick Bowler <nbowler@elliptictech.com>
      Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      da3e5150
  14. 31 3月, 2011 1 次提交
  15. 24 2月, 2011 1 次提交
  16. 09 8月, 2010 1 次提交