- 06 4月, 2009 1 次提交
-
-
由 Daniel Glöckner 提交于
According to the data sheet data is clocked out on the falling edge and latched on the rising edge of the bit clock. While the left sample is transmitted the word clock line is low. Signed-off-by: NDaniel Glöckner <dg@emlix.com> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
-
- 04 4月, 2009 1 次提交
-
-
由 Daniel Glöckner 提交于
This patch adds machine specific code for the audio part of the Stretch s6105 IP camera reference design. The device uses the tlv320aic31(01) codec to generate the clock for both I2S ports of the soc. While the master clock is generated by a configurable PLL chip, the code assumes the factory default settings. An additional kcontrol has been added to handle the special routing of the board, connecting both HPLCOM and HPROUT to the same pin of the audio jack. One of these should always be switched off. Signed-off-by: NDaniel Glöckner <dg@emlix.com> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
-